Inventor
SUGASAWARA EMERY O
US13 patents
Patents
13 patentsUS6189131B1Feb 13, 2001
Method of selecting and synthesizing metal interconnect wires in integrated circuits
LSI LOGIC CORP103 citations97
US6061814AMay 9, 2000
Test circuitry for determining the defect density of a semiconductor process as a function of individual metal layers
LSI LOGIC CORP135 citations97
US5972541AOct 26, 1999
Reticle and method of design to correct pattern for depth of focus problems
LSI LOGIC CORP96 citations97
US6124143ASep 26, 2000
Process monitor circuitry for integrated circuits
LSI LOGIC CORP81 citations95
US6185706B1Feb 6, 2001
Performance monitoring circuitry for integrated circuits
LSI LOGIC CORP53 citations92
US6097884AAug 1, 2000
Probe points and markers for critical paths and integrated circuits
LSI LOGIC CORP22 citations92
US6043672AMar 28, 2000
Selectable power supply lines for isolating defects in integrated circuits
LSI LOGIC CORP53 citations92
US5953518ASep 14, 1999
Yield improvement techniques through layout optimization
LSI LOGIC CORP19 citations87
US6278129B1Aug 21, 2001
Corrosion sensitivity structures for vias and contact holes in integrated circuits
LSI LOGIC CORP15 citations81
US6239609B1May 29, 2001
Reduced voltage quiescent current test methodology for integrated circuits
LSI LOGIC CORP16 citations75
US6103615AAug 15, 2000
Corrosion sensitivity structures for vias and contact holes in integrated circuits
LSI LOGIC CORP9 citations70
US6102962AAug 15, 2000
Method for estimating quiescent current in integrated circuits
LSI LOGIC CORP6 citations62
US7354790B2Apr 8, 2008
Method and apparatus for avoiding dicing chip-outs in integrated circuit die
LSI LOGIC CORP2 citations54