Inventor
GARVIN STACY J
US12 patents
Patents
12 patentsUS6031394AFeb 29, 2000
Low voltage CMOS circuit for on/off chip drive at high voltage
IBM67 citations96
US5396449AMar 7, 1995
Fast content addressable memory with reduced power consumption
IBM63 citations95
US4752699AJun 21, 1988
On chip multiple voltage generation using a charge pump and plural feedback sense circuits
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US4638464AJan 20, 1987
Charge pump system for non-volatile ram
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US7268613B2Sep 11, 2007
Transistor switch with integral body connection to prevent latchup
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US7042277B2May 9, 2006
Circuit and method for reducing jitter in a PLL of high speed serial links
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US6900703B2May 31, 2005
Method and system for adjusting a frequency range of a delay cell of a VCO
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US6977558B2Dec 20, 2005
Self-adaptive voltage regulator for a phase-locked loop
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US4536720AAug 20, 1985
Programmable oscillator with power down feature and frequency adjustment
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US7486127B2Feb 3, 2009
Transistor switch with integral body connection to prevent latchup
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US7539473B2May 26, 2009
Overshoot reduction in VCO calibration for serial link phase lock loop (PLL)
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US7279950B2Oct 9, 2007
Method and system for high frequency clock signal gating
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