Inventor

PARTSCH TORSTEN

US57 patents

⚠️ This page may combine multiple inventors who share the name “PARTSCH TORSTEN”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

PARTSCH TORSTEN

INFINEON TECHNOLOGIES AG

Methods and apparatus for implementing a power down in a memory device

Method of self-repairing dynamic random access memory

Method and apparatus for temperature throttling the access frequency of an integrated circuit

DQS postamble noise suppression by forcing a minimum pulse length

Delay locked loop for generating complementary clock signals

Synchronous integrated memory

Maintaining internal voltages of an integrated circuit in response to a clocked standby mode

Use of DQ pins on a ram memory chip for a temperature sensing protocol

Delay locked loop

Delay locked loop compensating for effective loads of off-chip drivers and methods for locking a delay loop

Method and apparatus for a delay lock loop

Semiconductor memory having a delay locked loop

Circuit and method for adjusting threshold drift over temperature in a CMOS receiver

Integrated memory having a row access controller for activating and deactivating row lines

Memory component with short access time

Circuit configuration for generating an output clock signal with optimized signal generation time

Integrated circuit for generating a phase-shifted output clock signal from a clock signal

Synchronous integrated memory

Integrated memory

Delay lock loop having an edge detector and fixed delay

Integrated circuit having a test operating mode and method for testing a multiplicity of such circuits

Method for on-die detection of the system operation frequency in a DRAM to adjust DRAM operations

Use of an on-die temperature sensing scheme for thermal protection of DRAMS

Indication of the system operation frequency to a DRAM during power-up

Memory device having off-chip driver enable circuit and method for reducing delays during read operations

Current mirror circuit

Circuit configuration for programming a delay in a signal path

RAMBUS INC

Memory component with input/output data rate alignment

Interconnect based address mapping for improved reliability

Memory component with input/output data rate alignment

Low power memory with on-demand bandwidth boost

Dynamic, random-access memory with hidden memory scrubbing

Row hammer mitigation

Quad-channel DRAM

Buffered dynamic random access memory device

Memory component with input/output data rate alignment

Memory component with programmable data-to-clock ratio

Joint command dynamic random access memory (DRAM) apparatus and methods

Buffered dynamic random access memory device

Low power memory control with on-demand bandwidth boost

Quad-channel DRAM

Low latency dynamic random access memory (DRAM) architecture with dedicated read-write data paths

Data destruction

DRAM security erase

Data-buffer controller/control-signal redriver

INFINEON TECHNOLOGIES CORP

Random access memory with post-amble data strobe signal noise rejection

Random access memory with optional inaccessible memory cells

SIEMENS AG

Integrated circuit with a phase locked loop

PARTSCH TORSTEN

Multi-chip package and interposer with signal line compression

INFINEON TECHNOLOGIES

Voltage generator with superimposed reference voltage and deactivation signals