Inventor

LA ROSA FRANCESCO

FR111 patents

⚠️ This page may combine multiple inventors who share the name “LA ROSA FRANCESCO”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

LA ROSA FRANCESCO

ST MICROELECTRONICS ROUSSET

Method for biasing an embedded source plane of a non-volatile memory having vertical select gates

Hot-carrier injection programmable memory and method of programming such a memory

Self-timed low power sense amplifier

Nonvolatile memory cells with a vertical selection gate of variable depth

Device for protecting an integrated circuit against back side attacks

Structure and method of forming a semiconductor device

Compact non-volatile memory device of the type with charge trapping in a dielectric interface

Memory cell comprising non-self-aligned horizontal and vertical control gates

Method for forming a PN junction and associated semiconductor device

Vertical bipolar transistor

Method and device for controlling a charge pump circuit

Method for fabricating an array of diodes, in particular for a non-volatile memory, and corresponding device

Memory cell comprising non-self-aligned horizontal and vertical control gates

Nonvolatile memory comprising mini wells at a floating potential

Non-volatile memory with vertical selection transistors

ST MICROELECTRONICS SA

Circuit for reading a charge retention element for a time measurement

Programmable POR circuit with two switching thresholds

EEPROM memory architecture

EEPROM memory protected against the effects from a breakdown of an access transistor

Current or voltage generator with a temperature stable operating point

EEPROM memory comprising means for simultaneous reading of special bits of a first and second type

Method for the correction of a bit in a string of bits

Bias circuit with voltage and temperature stable operating point

Circuit for the filtering of parasitic logic signals

Phase change memory erasable and programmable by a row decoder

Method for reading electrically programmable and erasable memory cells, with bit line precharge-ahead

Double read stage sense amplifier

Read amplifier with a low current consumption differential output stage

STMICROELECTRONICS ROUSSET

Dynamic sense amplifier with offset compensation

Memory cell comprising non-self-aligned horizontal and vertical control gates

Sense amplifier for memory device

Read performance of a non-volatile memory device, in particular a non-volatile memory device with buried selection transistor

Individually read-accessible twin memory cells

Dual non-volatile memory cell comprising an erase transistor

Method for programming a non-volatile memory cell comprising a shared select transistor gate

Vertical memory cell with non-self-aligned floating drain-source implant

Vertical memory cell with non-self-aligned floating drain-source implant

LA ROSA FRANCESCO

Circuit and method for detecting a fault attack

Electric charge flow circuit for a time measurement

Sense amplifier with fast bitline precharge means

EEPROM memory architecture optimized for embedded memories

Programming of a charge retention circuit for a time measurement

Charge retention circuit for a time measurement

EEPROM charge retention circuit for time measurement

Sense amplifier with fast bitline precharge means

ST MICROELECTRONICS SRL

Sense amplifier for non-volatile memory devices

Glitch immune ATD circuitry

Sense amplifier circuit with offset compensation for a non-volatile memory device

Dynamic sense amplifier for EPROM, EEPROM and flash-EPROM memory devices

Bitline bias circuit for non-volatile memory devices