Inventor
TAYLOR JR WILLIAM J
US48 patents
⚠️ This page may combine multiple inventors who share the name “TAYLOR JR WILLIAM J”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
GLOBALFOUNDRIES INC
16 patentsUS8889500B1Nov 18, 2014
Methods of forming stressed fin channel structures for FinFET semiconductor devices
GLOBALFOUNDRIES INC28 citations92
US8728885B1May 20, 2014
Methods of forming a three-dimensional semiconductor device with a nanowire channel structure
GLOBALFOUNDRIES INC31 citations92
US9362403B2Jun 7, 2016
Buried fin contact structures on FinFET semiconductor devices
GLOBALFOUNDRIES INC6 citations84
US9318552B2Apr 19, 2016
Methods of forming conductive contact structures for a semiconductor device with a larger metal silicide contact area and the resulting devices
GLOBALFOUNDRIES INC15 citations84
US9263340B2Feb 16, 2016
Methods for removing selected fins that are formed for finFET semiconductor devices
GLOBALFOUNDRIES INC11 citations84
US9202918B2Dec 1, 2015
Methods of forming stressed layers on FinFET semiconductor devices and the resulting devices
GLOBALFOUNDRIES INC13 citations84
US9153694B2Oct 6, 2015
Methods of forming contact structures on finfet semiconductor devices and the resulting devices
GLOBALFOUNDRIES INC10 citations84
US9461171B2Oct 4, 2016
Methods of increasing silicide to epi contact areas and the resulting devices
GLOBALFOUNDRIES INC4 citations73
US9312182B2Apr 12, 2016
Forming gate and source/drain contact openings by performing a common etch patterning process
GLOBALFOUNDRIES INC6 citations73
US8877588B2Nov 4, 2014
Methods of forming a three-dimensional semiconductor device with a dual stress channel and the resulting device
GLOBALFOUNDRIES INC4 citations73
US9299781B2Mar 29, 2016
Semiconductor devices with contact structures and a gate structure positioned in trenches formed in a layer of material
GLOBALFOUNDRIES INC2 citations63
US9231051B2Jan 5, 2016
Methods of forming spacers on FinFETs and other semiconductor devices
GLOBALFOUNDRIES INC2 citations63
US9171934B2Oct 27, 2015
Methods of forming semiconductor devices using a layer of material having a plurality of trenches formed therein
GLOBALFOUNDRIES INC2 citations63
US8962413B1Feb 24, 2015
Methods of forming spacers on FinFETs and other semiconductor devices
GLOBALFOUNDRIES INC0 citations52
US9330972B2May 3, 2016
Methods of forming contact structures for semiconductor devices and the resulting devices
GLOBALFOUNDRIES INC0 citations42
US9117930B2Aug 25, 2015
Methods of forming stressed fin channel structures for FinFET semiconductor devices
GLOBALFOUNDRIES INC0 citations41
MOTOROLA INC
9 patentsUS6362057B1Mar 26, 2002
Method for forming a semiconductor device
MOTOROLA INC313 citations99
US6514808B1Feb 4, 2003
Transistor having a high K dielectric and short gate length and method therefor
MOTOROLA INC104 citations98
US6362071B1Mar 26, 2002
Method for forming a semiconductor device with an opening in a dielectric layer
MOTOROLA INC149 citations98
US6849487B2Feb 1, 2005
Method for forming an electronic structure using etch
MOTOROLA INC93 citations96
US6475841B1Nov 5, 2002
Transistor with shaped gate electrode and method therefor
MOTOROLA INC32 citations92
US6423632B1Jul 23, 2002
Semiconductor device and a process for forming the same
MOTOROLA INC34 citations92
US6573160B2Jun 3, 2003
Method of recrystallizing an amorphous region of a semiconductor
MOTOROLA INC30 citations89
US6594422B2Jul 15, 2003
Opto-coupling device structure and method therefor
MOTOROLA INC11 citations71
US5633186AMay 27, 1997
Process for fabricating a non-volatile memory cell in a semiconductor device
MOTOROLA INC12 citations69
FREESCALE SEMICONDUCTOR INC
8 patentsUS7445981B1Nov 4, 2008
Method for forming a dual metal gate structure
FREESCALE SEMICONDUCTOR INC15 citations83
US7709331B2May 4, 2010
Dual gate oxide device integration
FREESCALE SEMICONDUCTOR INC7 citations73
US6849515B1Feb 1, 2005
Semiconductor process for disposable sidewall spacers
FREESCALE SEMICONDUCTOR INC10 citations73
US7179700B2Feb 20, 2007
Semiconductor device with low resistance contacts
FREESCALE SEMICONDUCTOR INC5 citations63
US7666730B2Feb 23, 2010
Method for forming a dual metal gate structure
FREESCALE SEMICONDUCTOR INC4 citations61
US7365410B2Apr 29, 2008
Semiconductor structure having a metallic buffer layer and method for forming
FREESCALE SEMICONDUCTOR INC4 citations61
US7544595B2Jun 9, 2009
Forming a semiconductor device having a metal electrode and structure thereof
FREESCALE SEMICONDUCTOR INC0 citations52
US7910442B2Mar 22, 2011
Process for making a semiconductor device using partial etching
FREESCALE SEMICONDUCTOR INC0 citations41
GLOBALFOUNDRIES US INC
5 patentsUS11855074B2Dec 26, 2023
Electrostatic discharge devices
GLOBALFOUNDRIES US INC0 citations62
US11543604B2Jan 3, 2023
On-chip heater with a heating element that locally generates different amounts of heat and methods
GLOBALFOUNDRIES US INC0 citations62
US11387353B2Jul 12, 2022
Structure providing charge controlled electronic fuse
GLOBALFOUNDRIES US INC0 citations62
US11435982B2Sep 6, 2022
True random number generation and physically unclonable functions using voltage control of magnetic anisotropy effects in STT-MRAM
GLOBALFOUNDRIES US INC0 citations50
US11934021B2Mar 19, 2024
Photonic devices integrated with thermally conductive layers
GLOBALFOUNDRIES US INC0 citations46
TAYLOR JR WILLIAM J
4 patentsUS4719700AJan 19, 1988
Knife opening mechanism
TAYLOR JR WILLIAM J147 citations98
US5331741AJul 26, 1994
Lever-actuated folding knife
TAYLOR JR WILLIAM J139 citations97
US4332097AJun 1, 1982
Drum magazine for automatic pistol or the like
TAYLOR JR WILLIAM J112 citations96
US4413546ANov 8, 1983
Drum magazine for carbines or the like
TAYLOR JR WILLIAM J48 citations92
IBM
3 patentsUS9583442B2Feb 28, 2017
Interconnect structure including middle of line (MOL) metal layer local interconnect on etch stop layer
IBM5 citations84
US9786607B2Oct 10, 2017
Interconnect structure including middle of line (MOL) metal layer local interconnect on ETCH stop layer
IBM2 citations73
US9728456B2Aug 8, 2017
Interconnect structure including middle of line (MOL) metal layer local interconnect on etch stop layer
IBM0 citations52