Inventor

ADETUTU OLUBUNMI O

US49 patents

⚠️ This page may combine multiple inventors who share the name “ADETUTU OLUBUNMI O”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

ADETUTU OLUBUNMI O

FREESCALE SEMICONDUCTOR INC

Semiconductor process and integrated circuit having dual metal oxide gate dielectric with single metal gate electrode

Method for treating a semiconductor surface to form a metal-containing layer

Process for forming dual metal gate structures

Multi-layer dielectric containing diffusion barrier material

Metal gate transistor CMOS process and method for making

Method for forming a layer using a purging gas in a semiconductor process

Process for forming dual metal gate structures

Modified hybrid orientation technology

SOI active layer with different surface orientation

Dual metal gate electrode semiconductor fabrication process and structure thereof

Low RC product transistors in SOI semiconductor process

Method for forming a gate electrode having a metal

Method of forming a gate dielectric by in-situ plasma

Method for removing metal foot during high-k dielectric/metal gate etching

Gate dielectric and metal gate integration

Method for forming a semiconductor device with local semiconductor-on-insulator (SOI)

Method of making a nitrided gate dielectric

Process of forming an electronic device including active regions and gate electrodes of different compositions overlying the active regions

Semiconductor process for forming stress absorbent shallow trench isolation structures

Dual metal silicide scheme using a dual spacer process

Method to control the gate sidewall profile by graded material composition

Electronic device comprising a gate electrode including a metal-containing layer having one or more impurities and a process for forming the same

Transitional dielectric layer to improve reliability and performance of high dielectric constant transistors

Method of forming a semiconductor device having a dielectric layer with high dielectric constant

Plasma treatment of a semiconductor surface for enhanced nucleation of a metal-containing layer

ALD gate electrode

Semiconductor device with low resistance contacts

Method of making a high quality thin dielectric layer

Method to reduce impurity elements during semiconductor film deposition

Electronic device comprising a gate electrode including a metal-containing layer having one or more impurities

Semiconductor device comprising a transistor having a counter-doped channel region and method for forming the same

Method of forming an arc layer for a semiconductor device

Plasma treatment of a semiconductor surface for enhanced nucleation of a metal-containing layer

In-situ nitridation of high-k dielectrics

Semiconductor device and method of forming the same

Film deposition on a semiconductor wafer

Method for forming floating gates within NVM process

Method of forming a via

MOTOROLA INC

Process for forming a high-K gate dielectric

Method of preventing two neighboring contacts from a short-circuit caused by a void between them and device having the same

Method for forming an electronic structure using etch

Transistor metal gate structure that minimizes non-planarity effects and method of formation

Method for forming a semiconductor device

Plated metal transistor gate and method of formation

ADETUTU OLUBUNMI O

Method of forming a shared contact in a semiconductor device

Modified hybrid orientation technology

Electronic device with a gate electrode having at least two portions

First inter-layer dielectric stack for non-volatile memory

TRIYOSO DINA H

Reverse ALD