Inventor

DREPS DANIEL MARK

US63 patents

⚠️ This page may combine multiple inventors who share the name “DREPS DANIEL MARK”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

DREPS DANIEL MARK

IBM

Dynamic wave-pipelined interface apparatus and methods therefor

Self-healing chip-to-chip interface

Cascaded differential receiver circuit

Smart memory interface

Selectable interface for interfacing integrated circuit modules

Low voltage CMOS differential amplifier

CMOS high-speed differential to single-ended converter circuit

Data processing system and method with dynamic idle for tunable interface calibration

Apparatus for connecting circuit modules

Method and apparatus for phase rotation in a phase locked loop

Method and apparatus for coupled phase locked loops

Low gain voltage-controlled oscillator

Noise generator for evaluating mixed signal integrated circuits

Elastic interface apparatus and method therefor

Dynamic duty cycle adjuster

Elastic interface apparatus and method therefor

Dynamic line termination clamping circuit

Method and system for data processing system self-synchronization

Sinusoidal clock signal distribution using resonant transmission lines

Method and apparatus for testing, characterizing and tuning a chip interface

Programmable delay circuit having a fine delay element selectively receives input signal and output signal of coarse delay element

Linear delay element providing linear delay steps

Self-healing chip-to-chip interface

System for latching first and second data on opposite edges of a first clock and outputting both data in response to a second clock

Elastic interface for master-slave communication

Variable voltage, variable impedance CMOS off-chip driver and receiver interface and circuits

Architecture for a physical interface of a high speed front side bus

Boundary scannable one bit precompensated CMOS driver with compensating pulse width control

Phase detector

Method and apparatus for interface signaling using single-ended and differential data signals

Clock generation apparatus and method for CMOS microprocessors using a differential saw oscillator

CMOS low voltage current reference

Method and system for data transfer

System for reducing cross-talk induced source synchronous bus clock jitter

Driver circuit having reduced noise

Dual duty cycle correction loop for a serializer/deserializer (SerDes) transmitter output

Modable dynamic terminator for high speed digital communications

Bus interface optimization by selecting bit-lanes having best performance margins

Programmable diagnostic memory module

Method for performing memory diagnostics using a programmable diagnostic memory module

Comparator and method for detecting a signal using a reference derived from a differential data signal pair

High speed differential CMOS sine-wave receiver with duty-cycle control means

Communication systems for power supply noise reduction

Quadrature circuit interconnect architecture with clock forwarding

Implementing phase rotator circuits with embedded polyphase filter network stage

Method for reducing cross-talk induced source synchronous bus clock jitter

Dynamically producing an effective impedance of an output driver with a bounded variation during transitions thereby reducing jitter

Multi-phase clock generation circuit with digital calibration

Architecture for a physical interface of a high speed front side bus

BICKFORD HARRY RANDALL

Variable voltage CMOS off-chip driver and receiver circuits