Inventor
BODA VEERABHADRA RAO
IN5 patents
Patents
5 patentsUS9928889B1Mar 27, 2018
Bitline precharge control and tracking scheme providing increased memory cycle speed for pseudo-dual-port memories
QUALCOMM INC17 citations84
US11152921B1Oct 19, 2021
Systems and methods for control signal latching in memories
QUALCOMM INC2 citations71
US9607674B1Mar 28, 2017
Pulse latch reset tracking at high differential voltage
QUALCOMM INC4 citations71
US10811086B1Oct 20, 2020
SRAM write yield enhancement with pull-up strength modulation
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US9865316B2Jan 9, 2018
Memory with a word line assertion delayed by a bit line discharge for write operations with improved write time and reduced write power
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