Inventor

LOVETT THOMAS D

US37 patents

⚠️ This page may combine multiple inventors who share the name “LOVETT THOMAS D”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

LOVETT THOMAS D

INTEL CORP

Method, apparatus, and system for QoS within high performance fabrics

Exascale fabric time synchronization

Reliable transport of ethernet packet data with wire-speed and packet data rate match

Method and system for flexible credit exchange within high performance fabrics

Technologies for synchronized sampling of counters based on a global clock

Technologies for high-performance network fabric security

Reliable transport of ethernet packet data with wire-speed and packet data rate match

Hierarchical/lossless packet preemption to reduce latency jitter in flow-controlled packet-based networks

Method and system for flexible credit exchange within high performance fabrics

Traffic class arbitration based on priority and bandwidth allocation

Performance monitoring

Traffic class arbitration based on priority and bandwidth allocation

Credit flow control for ethernet

Credit flow control for ethernet

Apparatus and method for buffering data in a switch

Apparatus and method for routing data in a switch

Apparatus and method for using multiple multi-drop buses

IBM

Method and system for communicating interrupts between nodes of a multinode computer system

Secure inter-node communication

Multiprocessor computer system with memory map translation

Maintaining order of write operations in a multiprocessor for memory consistency

Masterless building block binding to partitions using identifiers and indicators

Cache entry error-correcting code (ECC) based at least on cache entry data and memory address

Hardware support for partitioning a multiprocessor system to allow distinct operating systems

Different caching treatment of memory contents based on memory region

Multinode computer system with distributed clock synchronization system

Method and apparatus of using global snooping to provide cache coherence to distributed computer nodes in a single coherent system

Temporary storage of memory line while waiting for cache eviction

Multiple-stage pipeline for transaction conversion

Masterless building block binding to partitions

Coherency controller management of transactions

Building block removal from partitions

SEQUENT COMPUTER SYSTEMS INC

Method and apparatus for maintaining an order of write operations by processors in a multiprocessor computer to maintain memory consistency

Multinode computer system with cache for combined tags

Distributed shared memory system having a first node that prevents other nodes from accessing requested data until a processor on the first node controls the requested data

CHENG ALBERT S

Traffic class arbitration based on priority and bandwidth allocation

AT & T BELL LAB

Dual byte order data processor