Inventor

GRECO STEPHEN E

US54 patents

⚠️ This page may combine multiple inventors who share the name “GRECO STEPHEN E”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

GRECO STEPHEN E

IBM

Larce scale IC personalization method employing air dielectric structure for extended conductors

Chip interconnection having a breathable etch stop layer

Reliable low-k interconnect structure with hybrid dielectric

Increasing electromigration lifetime and current density in IC using vertically upwardly extending dummy via

Method for producing a crack stop for interlevel dielectric layers

Integrated circuit having crack stop for interlevel dielectric layers

Large scale IC personalization method employing air dielectric structure for extended conductor

Reliable low-k interconnect structure with hybrid dielectric

Fine-pitch device lithography using a sacrificial hardmask

Dual damascene flowable oxide insulation structure and metallic barrier

Cross-linked polyalkenyl phenol based photoresist compositions

Selective local metal cap layer formation for improved electromigration behavior

Via density change to improve wafer surface planarity

Increasing electromigration lifetime and current density in IC using vertically upwardly extending dummy via

Forming of local and global wiring for semiconductor product

Interconnect level structures for confining stitch-induced via structures

Generation of design shapes for confining stitch-induced via structures

Dry etchback of interconnect contacts

Method to generate porous organic dielectric

In situ formation of protective layer on silsesquioxane dielectric for dual damascene process

Interim oxidation of silsesquioxane dielectric for dual damascene process

Dual damascene flowable oxide insulation structure and metallic barrier

Selective local metal cap layer formation for improved electromigration behavior

Measuring metal line spacing in semiconductor devices

Selective local metal cap layer formation for improved electromigration behavior

Integrated circuit fuse

Integrated circuit fuse and method of opening

Dynamic metal fill for correcting non-planar region

System and method of predicting problematic areas for lithography in a circuit design

Laser fuse structures for high power applications

Dry etchback of interconnect contacts

Method to generate porous organic dielectric

Interim oxidation of silsesquioxane dielectric for dual damascene process

Intersect area based ground rule for semiconductor design

Method of annealing copper metallurgy

Multiple-depth trench interconnect technology at advanced semiconductor nodes

Early overlay prediction and overlay-aware mask design

Early overlay prediction and overlay-aware mask design

Multiple-depth trench interconnect technology at advanced semiconductor nodes

Interconnect level structures for confining stitch-induced via structures

Dividing lithography exposure fields to improve semiconductor fabrication

Selective local metal cap layer formation for improved electromigration behavior

GLOBALFOUNDRIES INC

Integrated circuit structure with metal crack stop and methods of forming same

Integrated circuit structure with crack stop and method of forming same

BRUNNER TIMOTHY A

System and method of predicting problematic areas for lithography in a circuit design

System and method of predicting problematic areas for lithography in a circuit design

GRECO NANCY A

Method of forming conductive lines and studs

MENTOR GRAPHICS CORP

System and method of predicting problematic areas for lithography in a circuit design

XIANG HUA

Apparatus, method and computer program product for fast simulation of manufacturing effects during integrated circuit design

CHIDAMBARRAO DURESETI

IC having viabar interconnection and related method