Inventor
BHATTACHARYYA BIDYUT K
US19 patents
⚠️ This page may combine multiple inventors who share the name “BHATTACHARYYA BIDYUT K”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
INTEL CORP
17 patentsUS5210939AMay 18, 1993
Lead grid array integrated circuit
INTEL CORP141 citations99
US4891687AJan 2, 1990
Multi-layer molded plastic IC package
INTEL CORP170 citations99
US5608261AMar 4, 1997
High performance and high capacitance package with improved thermal dissipation
INTEL CORP68 citations96
US5369545ANov 29, 1994
De-coupling capacitor on the top of the silicon die by eutectic flip bonding
INTEL CORP90 citations93
US5607883AMar 4, 1997
High performance and high capacitance package with improved thermal dissipation
INTEL CORP23 citations92
US5556807ASep 17, 1996
Advance multilayer molded plastic package using mesic technology
INTEL CORP26 citations92
US5420461AMay 30, 1995
Integrated circuit having a two-dimensional lead grid array
INTEL CORP37 citations92
US5666004ASep 9, 1997
Use of tantalum oxide capacitor on ceramic co-fired technology
INTEL CORP41 citations91
US6664620B2Dec 16, 2003
Integrated circuit die and/or package having a variable pitch contact array for maximization of number of signal lines per routing layer
INTEL CORP16 citations90
US5475565ADec 12, 1995
Power distribution lid for IC package
INTEL CORP30 citations89
US5773895AJun 30, 1998
Anchor provisions to prevent mold delamination in an overmolded plastic array package
INTEL CORP26 citations86
US4810671AMar 7, 1989
Process for bonding die to substrate using a gold/silicon seed
INTEL CORP15 citations73
US4771018ASep 13, 1988
Process of attaching a die to a substrate using gold/silicon seed
INTEL CORP7 citations73
US5307012AApr 26, 1994
Test substation for testing semi-conductor packages
INTEL CORP17 citations67
US5777265AJul 7, 1998
Multilayer molded plastic package design
INTEL CORP13 citations66
US7030479B2Apr 18, 2006
Integrated circuit die and/or package having a variable pitch contact array for maximization of number of signal lines per routing layer
INTEL CORP3 citations60
US5532983AJul 2, 1996
Circuit design for point-to-point chip for high speed testing
INTEL CORP4 citations58