Inventor

SUN SEY-SHING

US38 patents

⚠️ This page may combine multiple inventors who share the name “SUN SEY-SHING”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

SUN SEY-SHING

LSI LOGIC CORP

Method and structure for creating ultra low resistance damascene copper wiring

Carbon nanotube memory cell for integrated circuit structure with removable side spacers to permit access to memory cell and process for forming such memory cell

Damascene replacement metal gate process with controlled gate profile and length using Si1-xGex as sacrificial material

Method for creating barrier layers for copper diffusion

Nano structure electrode design

Method and structure for creating ultra low resistance damascene copper wiring

Reduce or eliminate IMC cracking in post wire bonded dies by doping aluminum used in bond pads during Cu/Low-k BEOL processing

Method for fabricating planar semiconductor wafers

Method and apparatus for redirecting void diffusion away from vias in an integrated circuit design

Incorporating dopants to enhance the dielectric properties of metal silicates

Bimetallic oxide compositions for gate dielectrics

Method for redirecting void diffusion away from vias in an integrated circuit design

PLANAR SYSTEMS INC

AC TFEL device having a white light emitting multilayer phosphor

TFEL device having multiple layer insulators

TFEL device with injection layer

Alternating current thin film electroluminescent device having blue light emitting alkaline earth phosphor

Electroluminescent phosphor thin films with increased brightness that includes an alkali halide

Multi-source reactive deposition process for the preparation of blue light emitting phosphor layers for AC TFEL devices

Electroluminescent alkaline-earth sulfide phosphor thin films with multiple coactivator dopants

Electroluminescent phosphor thin films

Thin film electroluminescent device

LSI CORP

Application of gate edge liner to maintain gate length CD in a replacement gate transistor flow

Integrated barrier and seed layer for copper interconnect technology

Bi-axial texturing of high-K dielectric films to reduce leakage currents

Method and apparatus for diverting void diffusion in integrated circuit conductors

Eliminate IMC cracking in post wirebonded dies: macro level stress reduction by modifying dielectric/metal film stack in be layers during Cu/Low-K processing

Application of gate edge liner to maintain gate length CD in a replacement gate transistor flow

Incorporating dopants to enhance the dielectric properties of metal silicates

Bi-axial texturing of high-K dielectric films to reduce leakage currents

(unassigned)

Oxygen-doped thiogallate phosphor

TFEL phosphor having metal overlayer

Alternating current thin film electroluminescent device having blue light emitting alkaline earth phosphor

KARPOV ELIJAH V

Low voltage embedded memory having conductive oxide and electrode stacks

Low voltage embedded memory having conductive oxide and electrode stacks

SUN SEY SHING

AC TFEL device having blue light emitting thiogallate phosphor

BHATT HEMANSHU

Alternate pad structures/passivation inegration schemes to reduce or eliminate IMC cracking in post wire bonded dies during Cu/Low-K BEOL processing

NANTERO INC

Self-aligned cell integration scheme

SUN SEY-SHING

Reduction of macro level stresses in copper/low-K wafers