Inventor
KOJIMA NOBUO
US12 patents
⚠️ This page may combine multiple inventors who share the name “KOJIMA NOBUO”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
IBM
9 patentsUS6578063B1Jun 10, 2003
5-to-2 binary adder
IBM26 citations92
US6437624B1Aug 20, 2002
Edge-triggered latch with symmetric complementary pass-transistor logic data path
IBM21 citations92
US6356990B1Mar 12, 2002
Set-associative cache memory having a built-in set prediction array
IBM45 citations92
US6584485B1Jun 24, 2003
4 to 2 adder
IBM18 citations83
US6453390B1Sep 17, 2002
Processor cycle time independent pipeline cache and method for pipelining data from a cache
IBM15 citations83
US6445217B1Sep 3, 2002
Edge-triggered latch with balanced pass-transistor logic trigger
IBM7 citations73
US6437625B1Aug 20, 2002
Edge triggered latch with symmetrical paths from clock to data outputs
IBM11 citations73
US6239620B1May 29, 2001
Method and apparatus for generating true/complement signals
IBM5 citations62
US6492856B1Dec 10, 2002
Edge triggered latch with symmetrical paths from clock to data outputs
IBM1 citations51