Inventor

BOGIN ZOHAR

US57 patents

⚠️ This page may combine multiple inventors who share the name “BOGIN ZOHAR”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

BOGIN ZOHAR

INTEL CORP

Apparatus and method for preventing access to SMRAM space through AGP addressing

Method and apparatus for dynamically placing portions of a memory in a reduced power consumtion state

Managing bus transaction dependencies

Inserting bus inversion scheme in bus path without increased access latency

Method and apparatus for dynamically placing portions of a memory in a reduced power consumption state

Method and apparatus for write cache flush and fill mechanisms

Method and apparatus to control core logic temperature

Method and apparatus for automatically correcting errors detected in a memory subsystem

Method and apparatus to control core logic temperature

Method and apparatus for control of power consumption in a computer system

Prefetch buffer allocation and filtering system

In order queue inactivity timer to improve DRAM arbiter operation

Avoiding deadlock by storing non-posted transactions in an auxiliary buffer when performing posted and non-posted bus transactions from an outbound pipe

Method and apparatus to control device temperature

Remapping I/O device addresses into high memory using GART

Method and apparatus for interrupt/SMI# ordering

Method and apparatus for processing interrupts of a bus

Abort of DRAM read ahead when PCI read multiple has ended

Method and system for servicing cache line in response to partial cache line request

Accelerated graphics port expedite cycle throttling control mechanism

Stream-down prefetching cache

Selective automatic precharge of dynamic random access memory banks

Tracking progress of data streamer

Arbitration methods to avoid deadlock and livelock when performing transactions across a bridge

Optimized memory addressing

AGP read and CPU wire coherency

Method and apparatus for interlocking a broadcast message on a bus

Stream under-run/over-run recovery

Method and apparatus for resource sharing in a multi-processor system

Method and apparatus for detecting an interruption in memory initialization

Method and apparatus for transmission of signals over a shared line

High performance chipset prefetcher for interleaved channels

Method and apparatus for a low latency source-synchronous address receiver for a host system bus in a memory controller

Method and apparatus for a low latency source-synchronous address receiver for a host system bus in a memory controller

Method to detect a temperature change by a thermal monitor and compensating for process, voltage, temperature effects caused by the temperature change

Dynamic update adaptive idle timer

Pending request scoreboard for out-of-order memory scheduler

Programmable multi-cycle signaling in integrated circuits

Power saving for isochronous data streams in a computer system

Managing bus transaction dependencies

Speculative request pointer advance for fast back-to-back reads

Method and apparatus for decoupling internal latencies of a bus bridge from those on an external bus

Stream under-run/over-run recovery

Apparatus and method for maintaining cache coherency in a memory system

Dynamically activated memory controller data termination

Avoiding livelock when performing a long stream of transactions

Method and apparatus for transmission of signals over a shared line

Method and apparatus for transmission of signals over a shared line

Dynamic adaptive read return of DRAM data

VEMBU BALAJI

Methods and apparatuses for securing playback content