Inventor
BISHOP JAMES WILSON
US12 patents
⚠️ This page may combine multiple inventors who share the name “BISHOP JAMES WILSON”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
IBM
7 patentsUS8380964B2Feb 19, 2013
Processor including age tracking of issue queue instructions
IBM18 citations90
US5809525ASep 15, 1998
Multi-level computer cache system providing plural cache controllers associated with memory address ranges and having cache directories
IBM20 citations87
US7631308B2Dec 8, 2009
Thread priority method for ensuring processing fairness in simultaneous multi-threading microprocessors
IBM12 citations84
US7254697B2Aug 7, 2007
Method and apparatus for dynamic modification of microprocessor instruction group at dispatch
IBM18 citations83
US7478276B2Jan 13, 2009
Method for checkpointing instruction groups with out-of-order floating point instructions in a multi-threaded processor
IBM4 citations62
US7620801B2Nov 17, 2009
Methods to randomly or pseudo-randomly, without bias, select instruction for performance analysis in a microprocessor
IBM1 citations51
US9110708B2Aug 18, 2015
Region-weighted accounting of multi-threaded processor core according to dispatch state
IBM0 citations49
BISHOP JAMES WILSON
4 patentsUS8103852B2Jan 24, 2012
Information handling system including a processor with a bifurcated issue queue
BISHOP JAMES WILSON34 citations90
US8418180B2Apr 9, 2013
Thread priority method for ensuring processing fairness in simultaneous multi-threading microprocessors
BISHOP JAMES WILSON6 citations83
US8489863B2Jul 16, 2013
Processor including age tracking of issue queue instructions
BISHOP JAMES WILSON5 citations70
US9015449B2Apr 21, 2015
Region-weighted accounting of multi-threaded processor core according to dispatch state
BISHOP JAMES WILSON0 citations48