Inventor
NGUYEN DUNG QUOC
US50 patents
⚠️ This page may combine multiple inventors who share the name “NGUYEN DUNG QUOC”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
IBM
42 patentsUS7290261B2Oct 30, 2007
Method and logical apparatus for rename register reallocation in a simultaneous multi-threaded (SMT) processor
IBM98 citations95
US8041928B2Oct 18, 2011
Information handling system with real and virtual load/store instruction issue queue
IBM46 citations94
US8046566B2Oct 25, 2011
Method to reduce power consumption of a register file with multi SMT support
IBM39 citations92
US7877580B2Jan 25, 2011
Branch lookahead prefetch for microprocessors
IBM41 citations92
US7421567B2Sep 2, 2008
Using a modified value GPR to enhance lookahead prefetch
IBM18 citations92
US7237094B2Jun 26, 2007
Instruction group formation and mechanism for SMT dispatch
IBM33 citations92
US7000047B2Feb 14, 2006
Mechanism for effectively handling livelocks in a simultaneous multithreading processor
IBM36 citations92
US7467325B2Dec 16, 2008
Processor instruction retry recovery
IBM26 citations91
US6275918B1Aug 14, 2001
Obtaining load target operand pre-fetch address from history table information upon incremented number of access indicator threshold
IBM32 citations91
US8380964B2Feb 19, 2013
Processor including age tracking of issue queue instructions
IBM18 citations90
US6463524B1Oct 8, 2002
Superscalar processor and method for incrementally issuing store instructions
IBM44 citations90
US7631308B2Dec 8, 2009
Thread priority method for ensuring processing fairness in simultaneous multi-threading microprocessors
IBM12 citations84
US7594096B2Sep 22, 2009
Load lookahead prefetch for microprocessors
IBM13 citations84
US6311267B1Oct 30, 2001
Just-in-time register renaming technique
IBM17 citations84
US6298435B1Oct 2, 2001
Methods and apparatus for exploiting virtual buffers to increase instruction parallelism in a pipelined processor
IBM16 citations84
US7827443B2Nov 2, 2010
Processor instruction retry recovery
IBM12 citations83
US7254697B2Aug 7, 2007
Method and apparatus for dynamic modification of microprocessor instruction group at dispatch
IBM18 citations83
US7600099B2Oct 6, 2009
System and method for predictive early allocation of stores in a microprocessor
IBM7 citations74
US6134645AOct 17, 2000
Instruction completion logic distributed among execution units for improving completion efficiency
IBM11 citations74
US10209995B2Feb 19, 2019
Processor core including pre-issue load-hit-store (LHS) hazard prediction to reduce rejection of load instructions
IBM5 citations73
US7444498B2Oct 28, 2008
Load lookahead prefetch for microprocessors
IBM6 citations73
US10223125B2Mar 5, 2019
Linkable issue queue parallel execution slice processing method
IBM3 citations72
US10133581B2Nov 20, 2018
Linkable issue queue parallel execution slice for a processor
IBM2 citations72
US10133576B2Nov 20, 2018
Parallel slice processor having a recirculating load-store queue for fast deallocation of issue queue entries
IBM2 citations72
US7243209B2Jul 10, 2007
Apparatus and method for speeding up access time of a large register file with wrap capability
IBM8 citations72
US6128722AOct 3, 2000
Data processing system having an apparatus for exception tracking during out-of-order operation and method therefor
IBM10 citations71
US8347068B2Jan 1, 2013
Multi-mode register rename mechanism that augments logical registers by switching a physical register from the register rename buffer when switching between in-order and out-of-order instruction processing in a simultaneous multi-threaded microprocessor
IBM2 citations63
US7302553B2Nov 27, 2007
Apparatus, system and method for quickly determining an oldest instruction in a non-moving instruction queue
IBM3 citations63
US6826678B2Nov 30, 2004
Completion monitoring in a processor having multiple execution units with various latencies
IBM2 citations63
US12061909B2Aug 13, 2024
Parallel slice processor having a recirculating load-store queue for fast deallocation of issue queue entries
IBM0 citations62
US11734010B2Aug 22, 2023
Parallel slice processor having a recirculating load-store queue for fast deallocation of issue queue entries
IBM0 citations62
US11150907B2Oct 19, 2021
Parallel slice processor having a recirculating load-store queue for fast deallocation of issue queue entries
IBM0 citations62
US7620799B2Nov 17, 2009
Using a modified value GPR to enhance lookahead prefetch
IBM2 citations62
US7552318B2Jun 23, 2009
Branch lookahead prefetch for microprocessors
IBM3 citations62
US7478276B2Jan 13, 2009
Method for checkpointing instruction groups with out-of-order floating point instructions in a multi-threaded processor
IBM4 citations62
US6535973B1Mar 18, 2003
Method and system for speculatively issuing instructions
IBM5 citations62
US7663963B2Feb 16, 2010
Apparatus and method for providing multiple reads/writes using a 2Read/2Write register file array
IBM2 citations61
US7650486B2Jan 19, 2010
Dynamic recalculation of resource vector at issue queue for steering of dependent instructions
IBM0 citations52
US7620801B2Nov 17, 2009
Methods to randomly or pseudo-randomly, without bias, select instruction for performance analysis in a microprocessor
IBM1 citations51
US7400548B2Jul 15, 2008
Method for providing multiple reads/writes using a 2read/2write register file array
IBM1 citations51
US7490226B2Feb 10, 2009
Method using vector component comprising first and second bits to regulate movement of dependent instructions in a microprocessor
IBM0 citations41
US7188233B2Mar 6, 2007
System and method for performing floating point store folding
IBM0 citations39