Inventor

CHEN JI-JAN

TW17 patents

⚠️ This page may combine multiple inventors who share the name “CHEN JI-JAN”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

CHEN JI-JAN

TAIWAN SEMICONDUCTOR MFG CO LTD

Phase-locked loop monitor circuit

Phase-locked loop monitor circuit

Phase-locked loop monitor circuit

Phase-locked loop monitor circuit

Device and method for robustness verification

Monolithic stacked integrated circuits with a redundant layer for repairing defects

Defect diagnosis

TSENG NAN-HSIN

Methods for detecting defect connections between metal bumps

Apparatus and method for on-chip sampling of dynamic IR voltage drop

CHUANG YI-LIN

Methods and apparatus for floorplanning and routing co-design

Method to determine optimal micro-bump-probe pad pairing for efficient PGD testing in interposer designs

IND TECH RES INST

Apparatus for clock skew compensation

Yield evaluating apparatus and method thereof

CHEN JI-JAN

Built-in self-test for interposer

LEE YU

Jitter measuring system and method

TAIWAN SEMICONDUCTOR MFG

Repairing monolithic stacked integrated circuits with a redundant layer and lithography process

LIU YEN-LING

Diagnosis framework to shorten yield learning cycles of advanced processes