Inventor

GUENTHNER RUSSELL W

US37 patents

⚠️ This page may combine multiple inventors who share the name “GUENTHNER RUSSELL W”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

GUENTHNER RUSSELL W

BULL HN INFORMATION SYST

Address transformation in a cluster computer system

System for explicitly referencing a register for its current content when performing processor context switch

Central processing unit using dual basic processing units and combined result bus

Processor with different width functional units ignoring extra bits of bus wider than instruction width

Safestore frame implementation in a central processor

Efficient error detection in a vlsi central processing unit

Store &#34;undo&#34; for cache store error recovery

Data processing system having a bus wider than processor instruction width

Associative memory system with a multi-digit incrementable validity counter

Central processing unit incorporation selectable, precisa ratio, speed of execution derating

Fast domain switch and error recovery in a secure CPU architecture

Basic operations synchronization and local mode controller in a VLSI central processor

Encapsulation of large native operating system functions as enhancements of the instruction set in an emulated central processor system

Performance improvement for software emulation of central processor unit utilizing signal handler

Data processing system utilizing multiple resister loading for fast domain switching

Instructions to load and store containing words in a computer system emulator with host word size larger than that of emulated machine

HONEYWELL INF SYSTEMS

Collector

Verification of real page numbers of stack stored prefetched instructions from instruction cache

Cache with independent addressable data and directory arrays

Method and apparatus for prefetching instructions for a central execution pipeline unit

Method and apparatus for calculating the residue of a signed binary number

Multiword data register array having simultaneous read-write capability

Dual address RAM

Clock pulse driver

One&#39;s complement adder

GUENTHNER RUSSELL W

Entering an identifier with security improved by time based randomization of input steps

Host computer system emulating target system legacy software and providing for incorporating more powerful application program elements into the flow of the legacy software

Method and apparatus providing COBOL decimal type arithmetic functions with improved performance

GUENTHNER CYNTHIA S

Method and apparatus for enabling parallel processing during execution of a Cobol source program using two-stage compilation

Method and apparatus enabling multi threaded program execution for a Cobol program including OpenMP directives by utilizing a two-stage compilation process

BULL HN INFORMATION SYSTEMS INC

Sorting/scanning system camera upgrade apparatus with backwards compatibility

Method for summarized viewing of large numbers of performance metrics while retaining cognizance of potentially significant deviations

HONEYWELL BULL

Prioritized secondary use of a cache with simultaneous access

WILHITE JOHN E

Method and apparatus for initiating the execution of instructions using a central pipeline execution unit

BULL INFORMATION SYSTEMS INC

Error detection in the basic processing unit of a VLSI central processor

KNEISEL TODD BRADLEY

Method for translating a cobol source program into readable and maintainable program code in an object oriented second programming language

BULL HN

Instructions providing new functionality for utilization by a target system program of host system container words during computer system emulation with host word size larger than that of the emulated machine

Store "undo" for cache store error recovery

One's complement adder