Inventor
HSU YARSUN
TW11 patents
⚠️ This page may combine multiple inventors who share the name “HSU YARSUN”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
IBM
9 patentsUS6094709AJul 25, 2000
Cache coherence for lazy entry consistency in lockup-free caches
IBM87 citations95
US5822763AOct 13, 1998
Cache coherence protocol for reducing the effects of false sharing in non-bus-based shared-memory multiprocessors
IBM89 citations95
US6175899B1Jan 16, 2001
Method for providing virtual atomicity in multi processor environment having access to multilevel caches
IBM23 citations92
US5778437AJul 7, 1998
Invalidation bus optimization for multiprocessors using directory-based cache coherence protocols in which an address of a line to be modified is placed on the invalidation bus simultaneously with sending a modify request to the directory
IBM31 citations92
US5287491AFeb 15, 1994
Network rearrangement method and system
IBM24 citations92
US5046000ASep 3, 1991
Single-FIFO high speed combining switch
IBM22 citations92
US4851995AJul 25, 1989
Programmable variable-cycle clock circuit for skew-tolerant array processor architecture
IBM39 citations92
US5313649AMay 17, 1994
Switch queue structure for one-network parallel processor systems
IBM24 citations90
US6148375ANov 14, 2000
Hierarchical bus simple COMA architecture for shared memory multiprocessors having a bus directly interconnecting caches between nodes
IBM7 citations73