Inventor
DAS DEBALEENA
US21 patents
⚠️ This page may combine multiple inventors who share the name “DAS DEBALEENA”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
INTEL CORP
11 patentsUS9691505B2Jun 27, 2017
Dynamic application of error correction code (ECC) based on error type
INTEL CORP21 citations94
US10496473B2Dec 3, 2019
Extracting selective information from on-die dynamic random access memory (DRAM) error correction code (ECC)
INTEL CORP11 citations84
US9811420B2Nov 7, 2017
Extracting selective information from on-die dynamic random access memory (DRAM) error correction code (ECC)
INTEL CORP7 citations84
US9760435B2Sep 12, 2017
Apparatus and method for generating common locator bits to locate a device or column error during error correction operations
INTEL CORP9 citations83
US9697094B2Jul 4, 2017
Dynamically changing lockstep configuration
INTEL CORP9 citations79
US10579464B2Mar 3, 2020
Method and apparatus for partial cache line sparing
INTEL CORP3 citations73
US9910728B2Mar 6, 2018
Method and apparatus for partial cache line sparing
INTEL CORP2 citations73
US9613722B2Apr 4, 2017
Method and apparatus for reverse memory sparing
INTEL CORP2 citations71
US8745464B2Jun 3, 2014
Rank-specific cyclic redundancy check
INTEL CORP3 citations61
US9904591B2Feb 27, 2018
Device, system and method to restrict access to data error information
INTEL CORP1 citations52
US10552643B2Feb 4, 2020
Fast boot up memory controller
INTEL CORP0 citations51
DAS DEBALEENA
3 patentsUS9195551B2Nov 24, 2015
Enhanced storage of metadata utilizing improved error detection and correction in computer memory
DAS DEBALEENA7 citations79
US12321898B2Jun 3, 2025
System and method for generating skill-centric online resumes with verifiable skills
DAS DEBALEENA0 citations49
US8914704B2Dec 16, 2014
Mechanism for achieving high memory reliablity, availability and serviceability
DAS DEBALEENA0 citations49