Inventor

HACHISUKA ATSUSHI

JP42 patents

⚠️ This page may combine multiple inventors who share the name “HACHISUKA ATSUSHI”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

HACHISUKA ATSUSHI

MITSUBISHI ELECTRIC CORP

Registration accuracy measurement mark, method of repairing defect of the mark, photomask having the mark, method of manufacturing the photo mask and method of exposure thereof

Method of manufacturing stacked capacitors in a DRAM with reduced isolation region between adjacent capacitors

Method of manufacturing a stacked capacitor in a dram

Dynamic random access memory having stacked type capacitor and manufacturing method therefor

Method of manufacturing a semiconductor memory device with multiple device forming regions

Method of manufacturing semiconductor device having interconnection layer contacting source/drain regions

Semiconductor memory device having a peripheral wall at the boundary region of a memory cell array region and a peripheral circuit region

Semiconductor device having interconnection layer contacting source/drain regions

Semiconductor device and method of manufacturing the same

Semiconductor device having a metallic fuse member and cutting method thereof with laser light

Field effect transistor having impurity regions of different depths and manufacturing method thereof

Method of forming a semiconductor memory device having a contact region between memory cell and an interlayer insolating layer

Semiconductor device having redundant circuit

Field effect transistor having impurity regions of different depths and manufacturing method thereof

Semiconductor memory device with contact region intermediate memory cell and peripheral circuit

Method of manufacturing a DRAM and logic device

Semiconductor device and a method of producing the same

Dynamic random access memory having stacked type capacitor and manufacturing method therefor

Field effect transistor having impurity regions of different depths and manufacturing method thereof

Registration accuracy measurement mark

Semiconductor device with sidewall insulating layers in the capacitor contact hole

Semiconductor memory device and method of manufacturing the same

Method of manufacturing a wiring layer for use in a semiconductor device having a plurality of conductive layers

Composite wiring layer

Semiconductor memory device having cylindrical capacitor and manufacturing method thereof

Method of making a semiconductor integrated device having gate sidewall structure

Semiconductor device having gate electrode spacing dependent upon gate side wall insulating dimension

Manufacturing method of a semiconductor device for desired circuit patterns

Registration accuracy measurement mark, method of repairing defect of the mark, photomask having the mark, method of manufacturing the photomask and method of exposure thereof

Semiconductor memory device having bit lines formed of an interconnecting layer of lower reflectance material than the material of the word lines

Method of manufacturing a semiconductor device having a stacked structure formed of polycrystalline silicon film and silicon oxide film

Method of making a semiconductor device with sidewall insulating layers in the capacitor contact hole

Method of manufacturing a semiconductor device having a cylindrical capacitor

Semiconductor device having contact between wiring layer and impurity region

Semiconductor device having a capacitor and method of manufacturing the same

Method for manufacturing a salicide transistor, semiconductor storage, and semiconductor device

RENESAS TECH CORP

Method for manufacturing semiconductor device and semiconductor device manufactured thereby

Semiconductor device and manufacturing method thereof

Semiconductor device and method of manufacturing same

Semiconductor device having interconnection structure

HACHISUKA ATSUSHI

Semiconductor device and method of manufacturing same

RENESAS ELECTRONICS CORP

Semiconductor device and method of manufacturing same