Inventor

EBIHARA HIROAKI

JP79 patents

⚠️ This page may combine multiple inventors who share the name “EBIHARA HIROAKI”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

EBIHARA HIROAKI

OMNIVISION TECH INC

Small pixels having dual conversion gain providing high dynamic range

Dual conversion gain high dynamic range readout for comparator of double ramp analog to digital converter

Image sensor with dual conversion gain readout

Ramp signal generator for double ramp analog to digital converter

Ramp signal settling reduction circuitry

Comparator stage with DC cut device for single slope analog to digital converter

Integrating ramp circuit with reduced ramp settling time

Dual conversion gain high dynamic range readout for comparator of double ramp analog to digital converter

Comparator output circuitry for single slope analog to digital converter

Bitline settling improvement by using dummy pixels for clamp

Comparator for double ramp analog to digital converter

Comparators for double ramp analog to digital converter

Bitline settling improvement and FPN reduction by floating bitline during charge transfer

Trimming control circuit for current integration ramp DAC settling assist circuit

Column amplifier capacitor switch circuit to adjust analog gain

Column amplifier reset circuit with comparator

CMOS image sensor clamping method with divided bit lines

Comparator for double ramp analog to digital converter

Comparator for double ramp analog to digital converter

Low noise CMOS image sensor by stack architecture

Bit line boost for fast settling with current source of adjustable size

Bitline boost for fast settling with current source of adjustable bias

Adaptive correlated multiple sampling

Ramp settling assist circuit in local ramp buffer circuit

Feedback capacitor and method for readout of hybrid bonded image sensors

Nine cell pixel image sensor with phase detection autofocus

Dual gain column structure for column power area efficiency

Two stage gray code counter with a redundant bit

Gray code counting signal distribution system

Adaptive correlated multiple sampling

Voltage domain global shutter readout circuit

Dual row select pixel for fast pixel binning

Layout design of dual row select structure

Adaptive data selection for DCG / DAG

Deep N-well driven ramp buffer

Dynamic current control for column ADC

EBIHARA HIROAKI

Solid state image capture device and camera system

Solid state image capture device and camera system

Solid-state image pickup device and camera system

Solid-state imaging element and camera system that determine in which horizontal read period a dummy pixel section is to be shuttered

Solid-state imaging device and camera system that controls a unit of plural rows

SONY CORP

Solid-state image pickup device and camera system

Solid-state image pickup device and camera system

Solid state imaging apparatus, signal reading method, and electronic apparatus

Solid state imaging element and camera system that determine in which horizontal read period a dummy pixel section is to be shuttered

Oscillator, oscillating method, image sensor, and imaging apparatus

SEIKO EPSON CORP

Electrostatic capacitance detection device and smart card

Electrostatic capacitance detection device

Capacitance detecting device

FUNATSU EIICHI

Solid-state image pickup device and camera system