Inventor
CODINA JOSEP M
ES12 patents
⚠️ This page may combine multiple inventors who share the name “CODINA JOSEP M”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
INTEL CORP
4 patentsUS7895415B2Feb 22, 2011
Cache sharing based thread control
INTEL CORP16 citations82
US10621092B2Apr 14, 2020
Merging level cache and data cache units having indicator bits related to speculative execution
INTEL CORP1 citations60
US9983880B2May 29, 2018
Method and apparatus for improved thread selection
INTEL CORP1 citations46
US10157063B2Dec 18, 2018
Instruction and logic for optimization level aware branch prediction
INTEL CORP0 citations36
LATORRE FERNANDO
2 patentsUS8909902B2Dec 9, 2014
Systems, methods, and apparatuses to decompose a sequential program into multiple threads, execute said threads, and reconstruct the sequential execution
LATORRE FERNANDO10 citations80
US8190652B2May 29, 2012
Achieving coherence between dynamically optimized code and original code
LATORRE FERNANDO4 citations60