Inventor

LIN YAOJIAN

SG310 patents

⚠️ This page may combine multiple inventors who share the name “LIN YAOJIAN”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

LIN YAOJIAN

STATS CHIPPAC LTD

Method of forming stress relief layer between die and interconnect structure

Semiconductor device and method of forming a vertical interconnect structure for 3-D FO-WLCSP

Semiconductor device and method of forming a vertical interconnect structure for 3-D FO-WLCSP

Semiconductor device and method of forming vertical interconnect structure with conductive micro via array for 3-D Fo-WLCSP

Semiconductor device and method of forming low profile 3D fan-out package

Solder bump with inner core pillar in semiconductor package

Wafer level die integration and method therefor

Semiconductor device and method of forming three-dimensional vertically oriented integrated capacitors

Semiconductor device and method of forming a 3D inductor from prefabricated pillar frame

Semiconductor device and method of forming the device using sacrificial carrier

Semiconductor package with semiconductor core structure and method of forming same

Semiconductor device and method of forming a shielding layer over a semiconductor die after forming a build-up interconnect structure

Semiconductor device having electrical devices mounted to IPD structure and method for shielding electromagnetic interference

Semiconductor device and method of forming high-frequency circuit structure and method thereof

Semiconductor device having wire studs as vertical interconnect in FO-WLP

Semiconductor device and method of forming interconnect structure for encapsulated die having pre-applied protective layer

Semiconductor device and method of forming interconnect structure for encapsulated die having pre-applied protective layer

Semiconductor device and method for forming passive circuit elements with through silicon vias to backside interconnect structures

Semiconductor device and method of forming embedded passive circuit elements interconnected to through hole vias

Semiconductor device and method of forming a fan-out PoP device with PWB vertical interconnect units

Semiconductor device and method of fabricating 3D package with short cycle time and high yield

Semiconductor device and method of forming a PoP device with embedded vertical interconnect units

Semiconductor device and method of forming PoP semiconductor device with RDL over top package

Semiconductor device and method of forming repassivation layer for robust low cost fan-out semiconductor package

Semiconductor device and method of forming microelectromechanical systems (MEMS) package

Semiconductor device and method of forming supporting layer over semiconductor die in thin fan-out wafer level chip scale package

Semiconductor device including integrated passive device formed over semiconductor die with conductive bridge and fan-out redistribution layer

System-in-package having integrated passive devices and method therefor

LIN YAOJIAN

Semiconductor device with a vertical interconnect structure for 3-D FO-WLCSP

Semiconductor package with semiconductor core structure and method of forming the same

Semiconductor device and method of forming interconnect substrate for FO-WLCSP

Semiconductor device and method of forming an embedded SOP fan-out package

Semiconductor device and method of forming a vertical interconnect structure for 3-D FO-WLCSP

Semiconductor method and device of forming a fan-out PoP device with PWB vertical interconnect units

Semiconductor package with semiconductor core structure and method of forming same

Semiconductor device and method of forming stacked vias within interconnect structure for Fo-WLCSP

Semiconductor device and method of forming sacrificial protective layer to protect semiconductor die edge during singulation

PAGAILA REZA A

Semiconductor device and method of forming RDL along sloped side surface of semiconductor die for z-direction interconnect

Semiconductor device and method of forming TSV semiconductor wafer with embedded semiconductor die

Semiconductor device and method of forming FO-WLCSP with discrete semiconductor components mounted under and over semiconductor die

Semiconductor device and method of forming interposer with opening to contain semiconductor die

Semiconductor device and method of forming openings in thermally-conductive frame of FO-WLCSP to dissipate heat and reduce package height

Semiconductor device and method of forming TMV and TSV in WLCSP using same carrier

Semiconductor device and method of forming stepped interposer for stacking and electrically connecting semiconductor die

STATS CHIPPAC PTE LTD

Semiconductor device and method of forming supporting layer over semiconductor die in thin fan-out wafer level chip scale package

Semiconductor device and method of forming build-up interconnect structures over a temporary substrate

Antenna in embedded wafer-level ball-grid array package

SHIM IL KWON

Semiconductor device and method of forming UBM fixed relative to interconnect structure for alignment of semiconductor die

Semiconductor device and method of forming interconnect structure for encapsulated die having pre-applied protective layer

HUANG RUI

Semiconductor device and method of forming no-flow underfill material around vertical interconnect structure