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Inventor

NOGUERA SERRA JUAN J

IE39 patents
⚠️ This page may combine multiple inventors who share the name “NOGUERA SERRA JUAN J”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

XILINX INC

36 patents
US10673439B1Jun 2, 2020

Adaptive integrated programmable device platform

XILINX INC77 citations98
US7973556B1Jul 5, 2011

System and method for using reconfiguration ports for power management in integrated circuits

XILINX INC90 citations98
US11063594B1Jul 13, 2021

Adaptive integrated programmable device platform

XILINX INC16 citations94
US10866753B2Dec 15, 2020

Data processing engine arrangement in a device

XILINX INC15 citations94
US11336287B1May 17, 2022

Data processing engine array architecture with memory tiles

XILINX INC26 citations93
US11288222B1Mar 29, 2022

Multi-die integrated circuit with data processing engine array

XILINX INC8 citations86
US10824584B1Nov 3, 2020

Device with data processing engine array that enables partial reconfiguration

XILINX INC13 citations85
US10747690B2Aug 18, 2020

Device with data processing engine array

XILINX INC19 citations85
US9189458B1Nov 17, 2015

Parameter estimation

XILINX INC16 citations84
US10635622B2Apr 28, 2020

System-on-chip interface architecture

XILINX INC10 citations83
US7932743B1Apr 26, 2011

Sequentially configurable programmable integrated circuit

XILINX INC13 citations78
US12001367B2Jun 4, 2024

Multi-die integrated circuit with data processing engine array

XILINX INC2 citations73
US11693808B2Jul 4, 2023

Multi-die integrated circuit with data processing engine array

XILINX INC3 citations73
US11573726B1Feb 7, 2023

Data processing engine arrangement in a device

XILINX INC1 citations73
US11567881B1Jan 31, 2023

Event-based debug, trace, and profile in device with data processing engine array

XILINX INC2 citations73
US11113223B1Sep 7, 2021

Dual mode interconnect

XILINX INC4 citations73
US11379389B1Jul 5, 2022

Communicating between data processing engines using shared memory

XILINX INC2 citations72
US11061673B1Jul 13, 2021

Data selection network for a data processing engine in an integrated circuit

XILINX INC2 citations72
US11016822B1May 25, 2021

Cascade streaming between data processing engines in an array

XILINX INC3 citations72
US10990552B1Apr 27, 2021

Streaming interconnect architecture for data processing engine array

XILINX INC4 citations72
US10747531B1Aug 18, 2020

Core for a data processing engine in an integrated circuit

XILINX INC3 citations72
US10579559B1Mar 3, 2020

Stall logic for a data processing engine in an integrated circuit

XILINX INC2 citations72
US12536132B2Jan 27, 2026

Data processing engine tile architecture for an integrated circuit

XILINX INC0 citations62
US12261603B2Mar 25, 2025

Adaptive integrated programmable device platform

XILINX INC0 citations62
US12105667B2Oct 1, 2024

Device with data processing engine array that enables partial reconfiguration

XILINX INC0 citations62
US11972132B2Apr 30, 2024

Data processing engine arrangement in a device

XILINX INC0 citations62
US11853235B2Dec 26, 2023

Communicating between data processing engines using shared memory

XILINX INC0 citations62
US11730325B2Aug 22, 2023

Dual mode interconnect

XILINX INC0 citations62
US11683038B1Jun 20, 2023

Adaptive integrated programmable device platform

XILINX INC0 citations62
US11372803B2Jun 28, 2022

Data processing engine tile architecture for an integrated circuit

XILINX INC1 citations62
US11599498B1Mar 7, 2023

Device with data processing engine array that enables partial reconfiguration

XILINX INC0 citations61
US12554310B2Feb 17, 2026

Power reduction in an array of data processing engines

XILINX INC0 citations58
US12555036B2Feb 17, 2026

Weight sparsity in data processing engines

XILINX INC0 citations52
US12505068B2Dec 23, 2025

Tiled compute and programmable logic array

XILINX INC0 citations51
US12067406B2Aug 20, 2024

Multiple overlays for use with a data processing array

XILINX INC0 citations45
US12164451B2Dec 10, 2024

Data processing array interface having interface tiles with multiple direct memory access circuits

XILINX INC0 citations44

LOTZE JORG

1 patent

COLLINS ANTHONY J

1 patent

MCANDREW DAVID

1 patent