Inventor
ENGLAND LUKE
US29 patents
⚠️ This page may combine multiple inventors who share the name “ENGLAND LUKE”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
GLOBALFOUNDRIES INC
18 patentsUS9536848B2Jan 3, 2017
Bond pad structure for low temperature flip chip bonding
GLOBALFOUNDRIES INC219 citations96
US10818570B1Oct 27, 2020
Stacked semiconductor devices having dissimilar-sized dies
GLOBALFOUNDRIES INC11 citations85
US9553080B1Jan 24, 2017
Method and process for integration of TSV-middle in 3D IC stacks
GLOBALFOUNDRIES INC12 citations84
US9257383B2Feb 9, 2016
Method and device for an integrated trench capacitor
GLOBALFOUNDRIES INC7 citations84
US10770440B2Sep 8, 2020
Micro-LED display assembly
GLOBALFOUNDRIES INC2 citations73
US9553058B1Jan 24, 2017
Wafer backside redistribution layer warpage control
GLOBALFOUNDRIES INC5 citations73
US9397073B1Jul 19, 2016
Method of using a back-end-of-line connection structure to distribute current envenly among multiple TSVs in a series for delivery to a top die
GLOBALFOUNDRIES INC5 citations73
US10083958B2Sep 25, 2018
Deep trench metal-insulator-metal capacitors
GLOBALFOUNDRIES INC2 citations72
US10636776B2Apr 28, 2020
Methods of manufacturing RF filters
GLOBALFOUNDRIES INC2 citations69
US10026883B2Jul 17, 2018
Wafer bond interconnect structures
GLOBALFOUNDRIES INC0 citations52
US9590028B2Mar 7, 2017
Method and device for an integrated trench capacitor
GLOBALFOUNDRIES INC0 citations52
US10381304B2Aug 13, 2019
Interconnect structure
GLOBALFOUNDRIES INC0 citations51
US10193011B1Jan 29, 2019
Method of manufacturing a 3 color LED integrated Si CMOS driver wafer using die to wafer bonding approach
GLOBALFOUNDRIES INC0 citations51
US10090227B1Oct 2, 2018
Back biasing in SOI FET technology
GLOBALFOUNDRIES INC0 citations49
US9466659B2Oct 11, 2016
Fabrication of multilayer circuit elements
GLOBALFOUNDRIES INC1 citations47
US10069490B2Sep 4, 2018
Method, apparatus and system for voltage compensation in a semiconductor wafer
GLOBALFOUNDRIES INC1 citations45
US10153224B2Dec 11, 2018
Backside spacer structures for improved thermal performance
GLOBALFOUNDRIES INC0 citations41
US10236263B1Mar 19, 2019
Methods and structures for mitigating ESD during wafer bonding
GLOBALFOUNDRIES INC0 citations37
APTINA IMAGING CORP
2 patentsENGLAND LUKE
2 patentsMARVELL ASIA PTE LTD
2 patentsUS12588470B2Mar 24, 2026
Methods for assembling stacked substrate packages including dies, laminated base substrates, and dielectric build-up substrates
MARVELL ASIA PTE LTD0 citations50
US12199003B2Jan 14, 2025
Packaging stacked substrates and an integrated circuit die using a lid and a stiffening structure
MARVELL ASIA PTE LTD0 citations47