Inventor

PAN HONG-TSZ

US35 patents

⚠️ This page may combine multiple inventors who share the name “PAN HONG-TSZ”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

PAN HONG-TSZ

UNITED MICROELECTRONICS CORP

Method of automatically generating dummy metals for multilevel interconnection

Method forming shallow trench isolation

Via sidewall SOG nitridation for via filling

Active layer mask with dummy pattern

Double rim phase shifter mask

Salicide formation process

Uniform field oxidation for locos isolation

Method of forming MOSFET devices with buried bitline capacitors

Process for forming high temperature stable self-aligned metal silicide layer

Method of reducing loss of metal silicide in pre-metal etching

Single polysilicon neuron MOSFET

Double destruction phase shift mask

Sealed vacuum electronic devices

Process for contact hole formation using a sacrificial SOG layer

Quantum chromeless lithography

Gap-filling process

Half-tone self-aligning phase shifting mask

Process for forming high temperature stable self-aligned metal silicide layer

Method for improving the planarization of dielectric layer in the fabrication of metallic interconnects

Salicide formation process

XILINX INC

Mitigation of well proximity effect in integrated circuits

Method of fabricating CMOS devices using fluid-based dielectric materials

Method and apparatus for compensating an integrated circuit layout for mechanical stress effects

Integrated circuit die with in-chip heat sink

Method and apparatus for suppressing metal-gate cross-diffusion in semiconductor technology

NEUROPREX INC

Devices and methods for magnetic stimulation for the treatment of neurological disorders

Devices and methods for magnetic stimulation for the treatment of neurological disorders

Devices and methods for magnetic stimulation for the treatment of neurological disorders

RAHMAN ARIFUR

Apparatus and method for testing of stacked die structure

Customizing metal pattern density in die-stacking applications

CHONG NUI

Embedded inductor

Systems and methods for electrostatic discharge protection

PAN HONG-TSZ

Apparatus and method for reducing plasma-induced damage in pMOSFETS

Integrated circuit structure having a capacitor structured to reduce dishing of metal layers

NGUYEN BANG-THU

System and method for detecting mask data handling errors