Inventor
REDDY LAKSHMI
US7 patents
Patents
7 patentsUS7581201B2Aug 25, 2009
System and method for sign-off timing closure of a VLSI chip
IBM35 citations90
US9703920B2Jul 11, 2017
Intra-run design decision process for circuit synthesis
IBM3 citations72
US10229238B2Mar 12, 2019
Congestion aware layer promotion
IBM0 citations51
US9690900B2Jun 27, 2017
Intra-run design decision process for circuit synthesis
IBM0 citations51
US9514265B2Dec 6, 2016
Congestion aware layer promotion
IBM1 citations51
US9495502B2Nov 15, 2016
Congestion aware layer promotion
IBM1 citations51
US10216882B2Feb 26, 2019
Critical path straightening system based on free-space aware and timing driven incremental placement
IBM0 citations36