Inventor
FETTERMAN MICHAEL ALAN
US17 patents
⚠️ This page may combine multiple inventors who share the name “FETTERMAN MICHAEL ALAN”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
NVIDIA CORP
11 patentsUS10699427B2Jun 30, 2020
Method and apparatus for obtaining sampled positions of texturing operations
NVIDIA CORP9 citations82
US10424074B1Sep 24, 2019
Method and apparatus for obtaining sampled positions of texturing operations
NVIDIA CORP7 citations82
US9600235B2Mar 21, 2017
Technique for performing arbitrary width integer arithmetic operations using fixed width elements
NVIDIA CORP9 citations82
US9471307B2Oct 18, 2016
System and processor that include an implementation of decoupled pipelines
NVIDIA CORP10 citations81
US9612836B2Apr 4, 2017
System, method, and computer program product for implementing software-based scoreboarding
NVIDIA CORP5 citations71
US10067768B2Sep 4, 2018
Execution of divergent threads using a convergence barrier
NVIDIA CORP2 citations69
US9477482B2Oct 25, 2016
System, method, and computer program product for implementing multi-cycle register file bypass
NVIDIA CORP4 citations69
US12417177B1Sep 16, 2025
Systems and methods for multicasting data
NVIDIA CORP0 citations44
US10489200B2Nov 26, 2019
Hierarchical staging areas for scheduling threads for execution
NVIDIA CORP0 citations41
US9477480B2Oct 25, 2016
System and processor for implementing interruptible batches of instructions
NVIDIA CORP0 citations41
US10503513B2Dec 10, 2019
Dispatching a stored instruction in response to determining that a received instruction is of a same instruction type
NVIDIA CORP0 citations38
INTEL CORP
6 patentsUS5812839ASep 22, 1998
Dual prediction branch system having two step of branch recovery process which activated only when mispredicted branch is the oldest instruction in the out-of-order unit
INTEL CORP118 citations97
US5903751AMay 11, 1999
Method and apparatus for implementing a branch target buffer in CISC processor
INTEL CORP38 citations96
US5768576AJun 16, 1998
Method and apparatus for predicting and handling resolving return from subroutine instructions in a computer processor
INTEL CORP75 citations96
US5944817AAug 31, 1999
Method and apparatus for implementing a set-associative branch target buffer
INTEL CORP27 citations91
US5778407AJul 7, 1998
Methods and apparatus for determining operating characteristics of a memory element based on its physical location
INTEL CORP35 citations91
US5706492AJan 6, 1998
Method and apparatus for implementing a set-associative branch target buffer
INTEL CORP22 citations91