Inventor
HEINRICH JENS
DE43 patents
⚠️ This page may combine multiple inventors who share the name “HEINRICH JENS”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
HEINRICH JENS
12 patentsUS8182709B2May 22, 2012
CMP system and method using individually controlled temperature zones
HEINRICH JENS11 citations83
US8138038B2Mar 20, 2012
Superior fill conditions in a replacement gate approach by performing a polishing process based on a sacrificial fill material
HEINRICH JENS8 citations81
US8716079B2May 6, 2014
Superior fill conditions in a replacement gate approach by corner rounding based on a sacrificial fill material
HEINRICH JENS6 citations69
US8877597B2Nov 4, 2014
Embedding metal silicide contact regions reliably into highly doped drain and source regions by a stop implantation
HEINRICH JENS2 citations62
US8492269B2Jul 23, 2013
Hybrid contact structure with low aspect ratio contacts in a semiconductor device
HEINRICH JENS2 citations62
US8338306B2Dec 25, 2012
Forming semiconductor resistors in a semiconductor device comprising metal gates by increasing etch resistivity of the resistors
HEINRICH JENS2 citations59
US9153684B2Oct 6, 2015
Semiconductor fuses in a semiconductor device comprising metal gates
HEINRICH JENS0 citations52
US8536052B2Sep 17, 2013
Semiconductor device comprising contact elements with silicided sidewall regions
HEINRICH JENS1 citations51
US8436425B2May 7, 2013
SOI semiconductor device comprising substrate diodes having a topography tolerant contact structure
HEINRICH JENS1 citations51
US8749330B2Jun 10, 2014
Electric contact element and method for producing an electric contact element
HEINRICH JENS1 citations46
US8329526B2Dec 11, 2012
Cap removal in a high-k metal gate electrode structure by using a sacrificial fill material
HEINRICH JENS0 citations41
US8922023B2Dec 30, 2014
Semiconductor device comprising metallization layers of reduced interlayer capacitance by reducing the amount of etch stop materials
HEINRICH JENS0 citations37
GLOBALFOUNDRIES INC
5 patentsUS8367504B2Feb 5, 2013
Method for forming semiconductor fuses in a semiconductor device comprising metal gates
GLOBALFOUNDRIES INC6 citations84
US7951677B2May 31, 2011
Corner rounding in a replacement gate approach based on a sacrificial fill material applied prior to work function metal deposition
GLOBALFOUNDRIES INC2 citations63
US7985668B1Jul 26, 2011
Method for forming a metal silicide having a lower potential for containing material defects
GLOBALFOUNDRIES INC6 citations62
US8383510B2Feb 26, 2013
Semiconductor device comprising metallization layers of reduced interlayer capacitance by reducing the amount of etch stop materials
GLOBALFOUNDRIES INC2 citations61
US8048726B2Nov 1, 2011
SOI semiconductor device with reduced topography above a substrate window area
GLOBALFOUNDRIES INC0 citations51
RICHTER RALF
4 patentsUS8951907B2Feb 10, 2015
Semiconductor devices having through-contacts and related fabrication methods
RICHTER RALF7 citations84
US8216928B1Jul 10, 2012
Methods for fabricating semiconductor devices having local contacts
RICHTER RALF4 citations62
US9034744B2May 19, 2015
Replacement gate approach for high-k metal gate stacks by avoiding a polishing process for exposing the placeholder material
RICHTER RALF0 citations42
US8658509B2Feb 25, 2014
Semiconductor resistors formed at a lower height level in a semiconductor device comprising metal gates
RICHTER RALF0 citations42
PHOENIX CONTACT GMBH & CO
3 patentsUS9275815B2Mar 1, 2016
Relay having two switches that can be actuated in opposite directions
PHOENIX CONTACT GMBH & CO37 citations91
US11177063B2Nov 16, 2021
Method for magnetising at least two magnets having different magnetic coercivity
PHOENIX CONTACT GMBH & CO0 citations62
US9368304B2Jun 14, 2016
Polarized electromagnetic relay and method for production thereof
PHOENIX CONTACT GMBH & CO0 citations42
SIEMENS AG
3 patentsSIEMENS ELECTROMECH COMPONENTS
2 patentsHUISINGA TORSTEN
2 patentsUS8786088B2Jul 22, 2014
Semiconductor device including ultra low-K (ULK) metallization stacks with reduced chip-package interaction
HUISINGA TORSTEN4 citations72
US8673770B2Mar 18, 2014
Methods of forming conductive structures in dielectric layers on an integrated circuit device
HUISINGA TORSTEN0 citations49