Inventor
ICHIKAWA HIROTAKA
JP9 patents
⚠️ This page may combine multiple inventors who share the name “ICHIKAWA HIROTAKA”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
TOSHIBA KK
6 patentsUS7194704B2Mar 20, 2007
Design layout preparing method
TOSHIBA KK61 citations97
US7266801B2Sep 4, 2007
Design pattern correction method and mask pattern producing method
TOSHIBA KK31 citations92
US7996794B2Aug 9, 2011
Mask data processing method for optimizing hierarchical structure
TOSHIBA KK8 citations79
US6964031B2Nov 8, 2005
Mask pattern generating method and manufacturing method of semiconductor apparatus
TOSHIBA KK7 citations73
US7998642B2Aug 16, 2011
Mask pattern data creation method and mask
TOSHIBA KK3 citations62
US7614026B2Nov 3, 2009
Pattern forming method, computer program thereof, and semiconductor device manufacturing method using the computer program
TOSHIBA KK0 citations41
TOSHIBA MEMORY CORP
3 patentsUS9977855B2May 22, 2018
Method of wiring layout, semiconductor device, program for supporting design of wiring layout, and method for manufacturing semiconductor device
TOSHIBA MEMORY CORP2 citations72
US9953126B2Apr 24, 2018
Method of wiring layout, semiconductor device, program for supporting design of wiring layout, and method for manufacturing semiconductor device
TOSHIBA MEMORY CORP4 citations72
US10852648B2Dec 1, 2020
Mask pattern correction system, and semiconductor device manufacturing method utilizing said correction system
TOSHIBA MEMORY CORP0 citations37