Inventor

HUTTON MICHAEL D

US73 patents

⚠️ This page may combine multiple inventors who share the name “HUTTON MICHAEL D”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

HUTTON MICHAEL D

ALTERA CORP

Programmable routing structures providing shorter timing delays for input/output signals

Register retiming technique

Method and apparatus for implementing additional registers in field programmable gate arrays to reduce design size

Register retiming technique

Physical resynthesis of a logic design

Using a timing exception to postpone retiming

Heterogeneous labs

Method and apparatus for implementing a field programmable gate array architecture with programmable clock skew

Programmable logic device having logic elements with dedicated hardware to configure look up tables as registers

Timing variation aware compilation

Method for adaptive critical path delay estimation during timing-driven placement for hierarchical programmable logic devices

Programmable logic devices with bidirect ional cascades

Register retiming technique

Performance visualization system

Configurable register circuitry for error detection and recovery

Error resilient packaged components

Memory blocks with shared address bus circuitry

Register retiming technique

Methods and apparatus for building bus interconnection networks using programmable interconnection resources

Time-multiplexed routing for reducing pipelining registers

Programmable logic device architecture with the ability to combine adjacent logic elements for the purpose of performing high order logic functions

Techniques for using edge masks to perform timing analysis

Clock distribution for specialized processing block in programmable logic device

Programmable logic device having complex logic blocks with improved logic cell functionality

Area efficient fractureable logic elements

Hybrid programmable many-core device with on-chip interconnect

Methods and tools for designing integrated circuits with auto-pipelining capabilities

Early timing estimation of timing statistical properties of placement

Organizations of logic modules in programmable logic devices

Techniques for using edge masks to perform timing analysis

Time-multiplexed routing in a programmable logic device architecture

Programmable logic device routing architecture to facilitate register re-timing

Field programmable gate array with integrated application specific integrated circuit fabric

Programmable logic device having logic elements with dedicated hardware to configure look up tables as registers

Configurable storage circuits with embedded processing and control circuitry

Timing control in a specialized processing block

User-accessible freeze-logic for dynamic power reduction and associated methods

Dedicated resource interconnects

Programmable routing structures providing shorter timing delays for input/output signals

Hybrid programmable many-core device with on-chip interconnect

HUTTON MICHAEL D

Field programmable gate array with integrated application specific integrated circuit fabric

Programmable logic device architecture with the ability to combine adjacent logic elements for the purpose of performing high order logic functions

Integrated circuits with interconnect selection circuitry

Early timing estimation of timing statistical properties of placement

Method and apparatus for performing parallel slack computation within a shared netlist region

Method and apparatus for implementing a field programmable gate array clock skew

Integrated circuits with shared interconnect buses

VAN ANTWERPEN BABETTE

Register retiming technique

Register retiming technique

SCHMIT HERMAN

Apparatus for field-programmable gate array with configurable architecture and associated methods