Inventor
SETHIA PRASHANT
IN11 patents
⚠️ This page may combine multiple inventors who share the name “SETHIA PRASHANT”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
CADENCE DESIGN SYSTEMS INC
10 patentsUS8863052B1Oct 14, 2014
System and method for generating and using a structurally aware timing model for representative operation of a circuit design
CADENCE DESIGN SYSTEMS INC44 citations93
US8788995B1Jul 22, 2014
System and method for guiding remedial transformations of a circuit design defined by physical implementation data to reduce needed physical corrections for detected timing violations in the circuit design
CADENCE DESIGN SYSTEMS INC55 citations93
US10776547B1Sep 15, 2020
Infinite-depth path-based analysis of operational timing for circuit design
CADENCE DESIGN SYSTEMS INC20 citations92
US10114920B1Oct 30, 2018
Method and apparatus for performing sign-off timing analysis of circuit designs using inter-power domain logic
CADENCE DESIGN SYSTEMS INC8 citations82
US9589096B1Mar 7, 2017
Method and apparatus for integrating spice-based timing using sign-off path-based analysis
CADENCE DESIGN SYSTEMS INC12 citations82
US10289774B1May 14, 2019
Systems and methods for reuse of delay calculation in static timing analysis
CADENCE DESIGN SYSTEMS INC9 citations81
US9633159B1Apr 25, 2017
Method and system for performing distributed timing signoff and optimization
CADENCE DESIGN SYSTEMS INC7 citations80
US9529962B1Dec 27, 2016
System and method for generating and using sibling nets model for shared delay calculation across multi-instantiated blocks in the circuit design
CADENCE DESIGN SYSTEMS INC6 citations71
US9405882B1Aug 2, 2016
High performance static timing analysis system and method for input/output interfaces
CADENCE DESIGN SYSTEMS INC6 citations69
US12423504B1Sep 23, 2025
Adaptive path based analysis process
CADENCE DESIGN SYSTEMS INC0 citations57