Inventor

POLIG RAPHAEL

CH22 patents

⚠️ This page may combine multiple inventors who share the name “POLIG RAPHAEL”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

POLIG RAPHAEL

IBM

Interposer for dynamic mapping of API calls

Deep neural network on field-programmable gate array

Native code generation for cloud services

Adaptable and extensible runtime and system for heterogeneous computer systems

Integrated circuit schematics having imbedded scaling information for generating a design instance

Random sequence generation for gene simulations

Interactive-aware clustering of stable states

Bit-serial linear algebra processor

Hardware compilation of cascaded grammars

Hardware compilation of cascaded grammars

Accelerated content analytics based on a hierarchical data-flow-graph representation

Defective memory column replacement with load isolation

Learning framework for software-hardware model generation and verification

Precision data access using differential data

Precision data access using differential data

Linear FE system solver with dynamic multi-grip precision

Adaptable and extensible runtime and system for heterogeneous computer systems

Index based memory access using single instruction multiple data unit

Non-deterministic finite state machine module for use in a regular expression matching system

SRAM array comprising multiple cell cores

CHAN YUEN H

Global bit line restore by most significant bit of an address line

WERNER TOBIAS

Method and system for generating a placement layout of a VLSI circuit design