P

Inventor

WERNER TOBIAS

DE40 patents
⚠️ This page may combine multiple inventors who share the name “WERNER TOBIAS”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

IBM

29 patents
US9406375B1Aug 2, 2016

Write address synchronization in 2 read/1write SRAM arrays

IBM16 citations83
US7557614B1Jul 7, 2009

Topology for a n-way XOR/XNOR circuit

IBM12 citations81
US11164879B2Nov 2, 2021

Microelectronic device with a memory element utilizing stacked vertical devices

IBM2 citations72
US10833089B2Nov 10, 2020

Buried conductive layer supplying digital circuits

IBM3 citations72
US7401312B2Jul 15, 2008

Automatic method for routing and designing an LSI

IBM5 citations62
US11328110B2May 10, 2022

Integrated circuit including logic circuitry

IBM0 citations61
US9437285B1Sep 6, 2016

Write address synchronization in 2 read/1write SRAM arrays

IBM2 citations61
US8918749B2Dec 23, 2014

Integrated circuit schematics having imbedded scaling information for generating a design instance

IBM3 citations61
US7546565B2Jun 9, 2009

Method for comparing two designs of electronic circuits

IBM2 citations60
US7936638B2May 3, 2011

Enhanced programmable pulsewidth modulating circuit for array clock generation

IBM6 citations59
US12575074B2Mar 10, 2026

Microelectronic device with stacked transistors

IBM0 citations53
US9537474B2Jan 3, 2017

Transforming a phase-locked-loop generated chip clock signal to a local clock signal

IBM0 citations52
US9401698B1Jul 26, 2016

Transforming a phase-locked-loop generated chip clock signal to a local clock signal

IBM1 citations52
US11171142B2Nov 9, 2021

Integrated circuit with vertical structures on nodes of a grid

IBM0 citations51
US10804266B2Oct 13, 2020

Microelectronic device utilizing stacked vertical devices

IBM0 citations51
US9837142B1Dec 5, 2017

Automated stressing and testing of semiconductor memory cells

IBM0 citations51
US9805823B1Oct 31, 2017

Automated stressing and testing of semiconductor memory cells

IBM0 citations51
US9627017B1Apr 18, 2017

RAM at speed flexible timing and setup control

IBM0 citations51
US9627090B1Apr 18, 2017

RAM at speed flexible timing and setup control

IBM0 citations51
US8964493B2Feb 24, 2015

Defective memory column replacement with load isolation

IBM1 citations51
US9997218B2Jun 12, 2018

Dual mode operation having power saving and active modes in a stacked circuit topology with logic preservation

IBM0 citations50
US9792967B1Oct 17, 2017

Managing semiconductor memory array leakage current

IBM1 citations50
US9786339B2Oct 10, 2017

Dual mode operation having power saving and active modes in a stacked circuit topology with logic preservation

IBM1 citations50
US9761289B1Sep 12, 2017

Managing semiconductor memory array leakage current

IBM0 citations50
US9711244B1Jul 18, 2017

Memory circuit

IBM0 citations50
US9904754B2Feb 27, 2018

Layout of interconnect lines in integrated circuits

IBM0 citations47
US9898571B2Feb 20, 2018

Layout of interconnect lines in integrated circuits

IBM0 citations47
US9384823B2Jul 5, 2016

SRAM array comprising multiple cell cores

IBM0 citations40
US8837235B1Sep 16, 2014

Local evaluation circuit for static random-access memory

IBM0 citations40

BOSCH GMBH ROBERT

3 patents

AVL MEDICAL INSTR AG

2 patents

AVL MEDICAL INSTR

2 patents

HOFFMANN LA ROCHE

2 patents

DJONGA CHRISTIAN

1 patent

WERNER TOBIAS

1 patent