P

Inventor

WOERNER ALEXANDER

DE11 patents
⚠️ This page may combine multiple inventors who share the name “WOERNER ALEXANDER”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

IBM

8 patents
US8375345B1Feb 12, 2013

Soft-bounded hierarchical synthesis

IBM21 citations91
US9058456B2Jun 16, 2015

Method and system to fix early mode slacks in a circuit design

IBM11 citations82
US7557614B1Jul 7, 2009

Topology for a n-way XOR/XNOR circuit

IBM12 citations81
US6292819B1Sep 18, 2001

Binary and decimal adder unit

IBM19 citations80
US7401312B2Jul 15, 2008

Automatic method for routing and designing an LSI

IBM5 citations62
US7546565B2Jun 9, 2009

Method for comparing two designs of electronic circuits

IBM2 citations60
US7490310B2Feb 10, 2009

Method for creating a layout for an electronic circuit

IBM4 citations52
US8964493B2Feb 24, 2015

Defective memory column replacement with load isolation

IBM1 citations51

BAROWSKI HARRY

1 patent
US8316335B2Nov 20, 2012

Multistage, hybrid synthesis processing facilitating integrated circuit layout

BAROWSKI HARRY10 citations82

KRAUCH ULRICH

1 patent
US8522182B2Aug 27, 2013

Generation of an end point report for a timing simulation of an integrated circuit

KRAUCH ULRICH3 citations55

WERNER TOBIAS

1 patent
US8631376B2Jan 14, 2014

Method and system for generating a placement layout of a VLSI circuit design

WERNER TOBIAS1 citations40