Inventor

YEN JOHNSON

US65 patents

⚠️ This page may combine multiple inventors who share the name “YEN JOHNSON”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

YEN JOHNSON

SK HYNIX INC

Techniques for low complexity turbo product code decoding

Techniques for adaptive LDPC decoding

High-speed low-power LDPC decoder design

Early selection decoding and automatic tuning

Data dependency mitigation in parallel decoders for flash storage

System and method for parallel decoding of codewords sharing common data

Techniques for low complexity soft decoder for turbo product codes

Hybrid soft decoding algorithm for multiple-dimension TPC codes

VSS LDPC decoder with improved throughput for hard decoding

Accelerated data copyback

Efficient data path architecture for flash devices configured to perform multi-pass programming

Efficient LDPC encoder for irregular code

Code reconstruction scheme for multiple code rate TPC decoder

Data mapping scheme for generalized product codes

HARATSCH ERICH F

Methods and apparatus for read-side intercell interference mitigation in flash memories

Methods and apparatus for soft demapping and intercell interference mitigation in flash memories

Methods and apparatus for programming multiple program values per signal level in flash memories

Methods and apparatus for write-side intercell interference mitigation in flash memories

Methods and apparatus for soft data generation for memory devices using decoder performance feedback

Methods and apparatus for soft data generation for memory devices

Methods and apparatus for soft data generation for memory devices based on performance factor adjustment

BROADCOM CORP

System and method generating a delayed clock output

Systems and methods for accessing preamp registers using commands via read channel/hard disk controller interface

Register exchange network for radix-4 SOVA (Soft-Output Viterbi Algorithm)

ACS (add compare select) implementation for radix-4 SOVA (soft-output viterbi algorithm)

Programmable inter-packet gap generator with byte granularity

Individually programmable most significant bits of VLAN ID

CHEN LEI

Multi-level LDPC layer decoder

Symbol flipping data processor

Mixed domain FFT-based non-binary LDPC decoder

Probability-based multi-level LDPC decoder

YEN JOHNSON

Systems and methods for evaluating and debugging LDPC iterative decoders

Systems and methods for accessing read channel registers using commands on data lines

Data processing system with out of order transfer

LSI CORP

Data recovery using no sync mark retry

LEH memory module architecture design in the multi-level LDPC coded iterative system

Hardware architecture and implementation of low power layered multi-level LDPC decoder

BURGER JR HARLEY F

Methods and apparatus for storing data in a multi-level cell flash memory device with cross-page sectors, multi-page coding and per-page coding

Methods and apparatus for soft data generation for memory devices based using reference cells

AGERE SYSTEMS LLC

Methods and apparatus for storing data in a multi-level cell flash memory device with cross-page sectors, multi-page coding and per-page coding

Methods and apparatus for storing data in a multi-level cell flash memory device with cross-page sectors, multi-page coding and per-page coding

GRAEF NILS

Methods and apparatus for intercell interference mitigation using modulation coding

SK HYNIX MEMORY SOLUTIONS INC

Memory controller and operating method thereof

KRACHKOVSKY VICTOR

Methods and apparatus for trellis-based modulation encoding

OLCAY SANCAR K

Symbol flipping LDPC decoding system

(unassigned)

Hanging decoration lamp with an active scenery

XIA HAITAO

Systems and methods for parity sharing data processing

LI ZONGWANG

Systems and methods for low density parity check data decoding

WANG CHUNG-LI

Multi-level LDPC layer decoder

KALLURI MADHUSUDAN

Systems and methods for enhanced accuracy NPML calibration