Inventor

SU JIANGHUI

US28 patents

⚠️ This page may combine multiple inventors who share the name “SU JIANGHUI”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

SU JIANGHUI

ORACLE INT CORP

Baseline wander correction gain adaptation

Configurable pulse amplitude modulation clock data recovery

Baud-rate clock data recovery with improved tracking performance

Fast direct feedback circuit for decision feedback equalization correction

Clock data recovery with increased frequency offset tracking

Post-cursor locking point adjustment for clock data recovery

Baseline wander correction using zero and one mismatch adaptation

At-rate SERDES clock data recovery with controllable offset

Adaptive receiver with pre-cursor cancelation

Adapative receiver with pre-cursor cancelation

Serdes fast retrain method upon exiting power saving mode

Method for duty cycle distortion detection through decision feedback equalizer taps

Adaptive receiver with pre-cursor cancelation

Calibration of clock path mismatches between data and error slicer

At-rate SERDES clock data recovery with controllable offset

Multi-rate finite impulse response filter

Precursor adaptation algorithm for asynchronously clocked SERDES

Method and apparatus for duty cycle distortion compensation

HUANG DAWEI

Clock-data recovery with non-zero h(−1) target

System and method of adapting precursor tap coefficient

Asymmetric decision feedback equalization slicing in high speed transceivers

SU JIANGHUI

Clock-data-recovery technique for high-speed links

Clock phase adjustment for a low-latency FIFO

VELODYNE LIDAR USA INC

Systems and methods for detecting an electromagnetic signal in a constant interference environment

Systems and methods for detecting an electromagnetic signal in a constant interference environment

ORACLE AMERICA INC

Assessment of on-chip circuit based on eye-pattern asymmetry

Apparatus and method for enabling an adaptation unit to be shared among a plurality of receivers

INTEGRATED DEVICE TECH

Multi-queue FIFO memory devices that support flow-through of write and read counter updates using multi-port flag counter register files