Inventor

BEHRENDS DERICK G

US35 patents

⚠️ This page may combine multiple inventors who share the name “BEHRENDS DERICK G”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

BEHRENDS DERICK G

IBM

Power management SRAM write bit line drive circuit

Power management domino SRAM bit line discharge circuit

Method and apparatus for multi-word write in domino read SRAMs

Circuit for improved SRAM write around with reduced read access penalty

Partial update in a ternary content addressable memory

Data security for dynamic random access memory using body bias to clear data at power-up

Method and apparatus to limit circuit delay dependence on voltage for single phase transition

Method and apparatus to limit circuit delay dependence on voltage

Design structure for improving performance of SRAM cells, SRAM cell, SRAM array, and write circuit

Method to improve performance of SRAM cells, SRAM cell, SRAM array, and write circuit

Methods and apparatus for testing integrated circuits

Glitch protect valid cell and method for maintaining a desired state value

Electrostatic discharge protection device with power management

Electrostatic discharge protection device with power management

Level shifter for a time-varying input

Level shifter for a time-varying input

Partial update in a ternary content addressable memory

Integrated decoupling capacitor utilizing through-silicon via

Integrated decoupling capacitor utilizing through-silicon via

Detecting maximum voltage between multiple power supplies for memory testing

Implementing enhanced performance dynamic evaluation circuit by combining precharge and delayed keeper

Implementing enhanced performance dynamic evaluation circuit by combining precharge and delayed keeper

Layout to minimize FET variation in small dimension photolithography

Assessing resources required to complete a VLSI design

Methods and apparatus for testing integrated circuits

On-chip diagnostic circuitry monitoring multiple cycles of signal samples

Memory array pulse width control

BEHRENDS DERICK G

Implementing mulitple mask lithography timing variation mitigation

Data dependent SRAM write assist

Implementing power saving self powering down latch structure

Implementing RC and coupling delay correction for SRAM

Data security for dynamic random access memory at power-up

Implementing single bit redundancy for dynamic SRAM circuit with any bit decode

Single cycle data copy for two-port SRAM

ADAMS CHAD A

High-speed testing of integrated devices