Inventor

NAYAR NARESH

US107 patents

⚠️ This page may combine multiple inventors who share the name “NAYAR NARESH”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

NAYAR NARESH

IBM

Event-driven communications interface for logically-partitioned computer

High performance synchronization of resource allocation in a logically-partitioned system

Apparatus and method for virtualizing interrupts in a logically partitioned computer system

Processor reset generated via memory access interrupt

Virtualization of a global interrupt queue

Virtualization of a global interrupt queue

Method and apparatus for autonomic policy-based thermal management in a data processing system

Management of a concurrent use license in a logically-partitioned computer

Logical partition manager and method

Method and apparatus for allocating processor resources in a logically partitioned computer system

Method and apparatus for coordinating dynamic memory deallocation with a redundant bit line steering mechanism

Allocating entitled processor cycles for preempted virtual processors

Dynamic switching of multithreaded processor between single threaded and simultaneous multithreaded modes

Managing paging I/O errors during hypervisor page fault processing

Method for autonomic workload distribution on a multicore processor

Live migration of a logical partition

Apparatus and method for selectively invalidating entries in an address translation cache

Transparent replacement of a failing processor

Technique for using shared resources on a multi-threaded processor

System and method for updating a time-related state of a migrating logical partition

Method and apparatus to monitor the run state of a multi-partitioned computer system

Dynamic diagnostic program for determining thread wait time

Tracking modifications to a virtual machine image that occur during backup of the virtual machine

Tracking modifications to a virtual machine image that occur during backup of the virtual machine

Managing CPU resources for high availability micro-partitions

Virtual machines failover

Transparently increasing power savings in a power management environment

Assigning a processor to a logical partition

Controlling an operational mode for a logical partition on a computing system

Power-aware line intervention for a multiprocessor snoop coherency protocol

Method, apparatus, and product for an efficient virtualized time base in a scaleable multi-processor computer

Assigning a processor to a logical partition

Replacing a failing physical processor

Method and apparatus for selecting the architecture level to which a processor appears to conform

Information handling system including dynamically merged physical partitions

System for yielding to a processor

Yield on multithreaded processors

System and method for tracking the memory state of a migrating logical partition

System quiesce for concurrent code updates

ARMSTRONG WILLIAM J

Entitlement management system, method and program product for resource allocation among micro-partitions

Transparent update of adapter firmware for self-virtualizing input/output device

Multiple partition adjunct instances interfacing multiple logical partitions to a self-virtualizing input/output device

HEYRMAN PETER JOSEPH

Partition transparent memory error handling in a logically partitioned computer system with mirrored memory

Partition transparent correctable error handling in a logically partitioned computer system

JACOBS STUART Z

Transparent hypervisor pinning of critical memory areas in a shared memory partition data processing system

FLOYD MICHAEL S

Performing virtual and/or physical resource management for power management

FRAZIER GILES R

Privilege level aware processor hardware resource management facility

ARMSTRONG WILLIAM JOSEPH

Dynamic switching of multithreaded processor between single threaded and simultaneous multithreaded modes

ARNDT RICHARD LOUIS

Controlling depth and latency of exit of a virtual processor&#39;s idle state in a power management environment

O'CONNOR JAMES A

Methods, systems, and computer program products for dynamic selective memory mirroring

Controlling depth and latency of exit of a virtual processor's idle state in a power management environment