Inventor

TAKAHASHI RICHARD J

US41 patents

⚠️ This page may combine multiple inventors who share the name “TAKAHASHI RICHARD J”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

TAKAHASHI RICHARD J

SECTURION SYSTEMS INC

Multi-level independent security architecture

Multi-tenancy architecture

Secure end-to-end communication system

Security device with programmable systolic-matrix cryptographic module and programmable input/output interface

Multi-level independent security architecture

Systolic random number generator

Multi-tenancy architecture

Client(s) to cloud or remote server secure data or file object encryption gateway

Security device with programmable systolic-matrix cryptographic module and programmable input/output interface

Secure end-to-end communication system

Multi-tenancy architecture

Security device with programmable systolic-matrix cryptographic module and programmable input/output interface

Replaceable or removable physical interface input/output module

Cloud storage using encryption gateway with certificate authority identification

Security device with programmable systolic-matrix cryptographic module and programmable input/output interface

Multi-tenancy architecture

Multi-level independent security architecture

Systolic random number generator

Multi-independent level secure (MILS) storage encryption

Secure data transfer over wireless networks using data storage encryptors

Systolic random number generator

Cloud storage using encryption gateway with certificate authority identification

Multi-independent level security for high performance computing and data storage systems

Multi-independent level security for high performance computing and data storage systems

INTEL CORP

Protection of information transmitted over communications channels

Protecting information in a system

Providing telephony services

Secure communication over a link

Processor-based system

Processor-based system

CORRENT CORP

Circuit and method for performing multiple modulo mathematic operations

Method and system for a full-adder post processor for modulo arithmetic

Pipelined digital randomizer based on permutation and substitution using data sampling with variable frequency and non-coherent clock sources

TAKAHASHI RICHARD J

Circuit and method for performing multiple modulo mathematic operations

Trusted tamper reactive secure storage

Method and system for embedding security in a mobile communications device

VLSI TECHNOLOGY INC

Dual purpose security architecture with protected internal operating system

Digital randomizer for on-chip generation and storage of random self-programming data block

ITT MFG ENTERPRISES INC

Computer input/output (I/O) connector assembly having a security circuit disposed therein

Circuit and method for performing multiple modulo mathematic operations

CYBER SOLUTIONS INT LLC

Trusted tamper reactive secure storage