Inventor

MUFF ADAM J

US73 patents

⚠️ This page may combine multiple inventors who share the name “MUFF ADAM J”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

MUFF ADAM J

IBM

Instruction set architecture with opcode lookup using memory attribute

Execution of a sequence of vector instructions preceded by a swizzle sequence instruction specifying data element shuffle orders respectively

Load latency speculation in an out-of-order computer processor

Extensible execution unit interface architecture with multiple decode logic and multiple execution units

Indirect instruction predication

Indirect instruction predication

Extensible execution unit interface architecture with multiple decode logic and multiple execution units

Concurrent multiple instruction issue of non-pipelined instructions using non-pipelined operation resources in another processing core

Local instruction loop buffer utilizing execution unit register file

Instruction set architecture with secure clear instructions for protecting processing unit architected state information

Instruction set architecture with secure clear instructions for protecting processing unit architected state information

Fault tolerant stability critical execution checking using redundant execution pipelines

Streaming direct inter-thread communication buffer packets that support hardware controlled arbitrary vector operand alignment in a densely threaded network on a chip

Branch prediction with power usage prediction and control

Branch prediction with power usage prediction and control

Instruction set architecture with opcode lookup using memory attribute

Instruction set architecture with opcode lookup using memory attribute

Extensible execution unit interface architecture with multiple decode logic and multiple execution units

Floating point execution unit for calculating packed sum of absolute differences

Floating point execution unit for calculating packed sum of absolute differences

Local instruction loop buffer utilizing execution unit register file

Local instruction loop buffer utilizing execution unit register file

Floating point execution unit for calculating packed sum of absolute differences

Floating point execution unit for calculating packed sum of absolute differences

Branch prediction with power usage prediction and control

Extensible execution unit interface architecture with multiple decode logic and multiple execution units

Indirect instruction predication

Local instruction loop buffer utilizing execution unit register file

Indirect instruction predication

Dynamic range adjusting floating point execution unit

Power reduction by minimizing bit transitions in the hamming distances of encoded communications

Translation management instructions for updating address translation data structures in remote processing nodes

Vector execution unit with prenormalization of denormal values

Vector execution unit with prenormalization of denormal values

MUFF ADAM J

Virtualization support for branch prediction logic enable / disable at hypervisor and guest operating system levels

Memory address translation-based data encryption with integrated encryption engine

Memory address translation-based data encryption/compression

Instruction predication using instruction filtering

Instruction predication using unused datapath facilities

Direct interthread communication dataport pack/unpack and load/save

System and method for selectively saving and restoring state of branch prediction logic through separate hypervisor-mode and guest-mode and/or user-mode instructions

Trigonometric summation vector execution unit

HICKEY MARK J

Floating point execution unit with fixed point functionality

Fault tolerant stability critical execution checking using redundant execution pipelines

Dynamic range adjusting floating point execution unit

Detecting logically non-significant operation based on opcode and operand and setting flag to decode address specified in subsequent instruction as different address

GLOBALFOUNDRIES INC

Multi-petascale highly efficient parallel supercomputer

Instruction set architecture with extensible register addressing

General purpose processing unit with low power digital signal processing (DSP) mode

ASAAD SAMEH

Multi-petascale highly efficient parallel supercomputer