Inventor

TUBBS MATTHEW R

US88 patents

⚠️ This page may combine multiple inventors who share the name “TUBBS MATTHEW R”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

TUBBS MATTHEW R

IBM

Instruction set architecture with opcode lookup using memory attribute

Execution of a sequence of vector instructions preceded by a swizzle sequence instruction specifying data element shuffle orders respectively

Pre-loading context states by inactive hardware thread in advance of context switch

Extensible execution unit interface architecture with multiple decode logic and multiple execution units

Indirect instruction predication

Indirect instruction predication

Extensible execution unit interface architecture with multiple decode logic and multiple execution units

Local instruction loop buffer utilizing execution unit register file

Concurrent multiple instruction issue of non-pipelined instructions using non-pipelined operation resources in another processing core

Instruction set architecture with secure clear instructions for protecting processing unit architected state information

Instruction set architecture with secure clear instructions for protecting processing unit architected state information

Fault tolerant stability critical execution checking using redundant execution pipelines

Streaming direct inter-thread communication buffer packets that support hardware controlled arbitrary vector operand alignment in a densely threaded network on a chip

Branch prediction with power usage prediction and control

Branch prediction with power usage prediction and control

Instruction set architecture with opcode lookup using memory attribute

Instruction set architecture with opcode lookup using memory attribute

Floating point execution unit for calculating packed sum of absolute differences

Extensible execution unit interface architecture with multiple decode logic and multiple execution units

Floating point execution unit for calculating packed sum of absolute differences

Local instruction loop buffer utilizing execution unit register file

Local instruction loop buffer utilizing execution unit register file

Floating point execution unit for calculating packed sum of absolute differences

Floating point execution unit for calculating packed sum of absolute differences

Branch prediction with power usage prediction and control

Extensible execution unit interface architecture with multiple decode logic and multiple execution units

Local instruction loop buffer utilizing execution unit register file

Indirect instruction predication

Indirect instruction predication

Dynamic range adjusting floating point execution unit

Power reduction by minimizing bit transitions in the hamming distances of encoded communications

MEJDRICH ERIC O

Performance event triggering through direct interthread communication on a network on chip

Single step mode in a software pipeline within a highly threaded network on a chip microprocessor

Instruction buffer bypass of target instruction in response to partial flush

DMA-based acceleration of command push buffer between host and target devices

Parallelized ray tracing

Multithreaded software rendering pipeline with dynamic performance-based reallocation of raster threads

Propagating shared state changes to multiple threads within a multithreaded processing environment

Sequential processing in network on chip nodes by threads generating message containing payload and pointer for nanokernel to access algorithm to be executed on payload in another node

MUFF ADAM J

Virtualization support for branch prediction logic enable / disable at hypervisor and guest operating system levels

Memory address translation-based data encryption with integrated encryption engine

Memory address translation-based data encryption/compression

Instruction predication using instruction filtering

Instruction predication using unused datapath facilities

Direct interthread communication dataport pack/unpack and load/save

HICKEY MARK J

Floating point execution unit with fixed point functionality

Dynamic range adjusting floating point execution unit

Fault tolerant stability critical execution checking using redundant execution pipelines

GLOBALFOUNDRIES INC

Instruction set architecture with extensible register addressing

General purpose processing unit with low power digital signal processing (DSP) mode