Inventor

VAN BUSKIRK MICHAEL A

US68 patents

⚠️ This page may combine multiple inventors who share the name “VAN BUSKIRK MICHAEL A”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

VAN BUSKIRK MICHAEL A

ADVANCED MICRO DEVICES INC

Source side sensing scheme for virtual ground read of flash eprom array with adjacent bit precharge

Planar structure for non-volatile memory devices

Drain side sensing scheme for virtual ground flash EPROM array with adjacent bit charge and hold

Method of simultaneous formation of bitline isolation and periphery oxide

Non-volatile memory array that enables simultaneous read and write operations

Method for measuring VT &#39;s less than zero without applying negative voltages

Flash EEPROM array with paged erase architecture

Temperature-compensated bias generator

Memory architecture for a three volt flash EEPROM

Flash EEPROM array with high endurance

Flash EEPROM array with negative gate voltage erase operation

Method of fabricating double densed core gates in sonos flash memory

Simultaneous formation of charge storage and bitline to wordline isolation

Simultaneous formation of charge storage and bitline to wordline isolation

Method for eliminating of cycling-induced electron trapping in the tunneling oxide of 5 volt only flash EEPROMS

Independent array grounds for flash EEPROM array with paged erase architechture

Sector-based redundancy architecture

VPP power supply having a regulator circuit for controlling a regulated positive potential

Drain power supply

High voltage charge pumps with series capacitors

Output buffer arrangement for reducing chip noise without speed penalty

Flash memory array with dual function control lines and asymmetrical source and drain junctions

Single bit array edges

Distributed negative gate power supply

Flash eeprom array with improved high endurance

Negative power supply

Sense circuit for a flash eefprom cell having a negative delta threshold voltage

Method of inhibiting degradation of ultra short channel charge-carrying devices during discharge

System and method for multi-bit flash reads using dual dynamic references

Method and low-power circuits used to generate accurate drain voltage for flash memory core cells in read mode

Flash memory array with dual function control lines and asymmetrical source and drain junctions

Process for fabricating a flash memory with dual function control lines

Power-on reset circuit

CYPRESS SEMICONDUCTOR CORP

NAND memory cell string having a stacked select gate structure and process for for forming same

NAND memory cell string having a stacked select gate structure and process for for forming same

NAND memory cell string having a stacked select gate structure and process for for forming same

ADESTO TECHNOLOGIES CORP

Circuits and methods for programming variable impedance elements

Latch circuits and methods with programmable impedance elements

Resistive switching memory

SPANSION LLC

Variable density and variable persistent organic memory devices, methods, and fabrication

Memory device and methods of using and making the device

Use of periodic refresh in medium retention memory arrays

VAN BUSKIRK MICHAEL A

Techniques for providing a direct injection semiconductor memory device

Semiconductor memory device

BANNA SRINIVASA RAO

Semiconductor memory device and method for biasing same

Techniques for providing a semiconductor memory device

CARMAN ERIC S

Techniques for providing a direct injection semiconductor memory device having ganged carrier injection lines

INTEL CORP

Virtual ground memory

ADESTO TECH CORP

Resistive switching memory

SIERRA SEMICONDUCTOR CORP

Electrically alterable non-volatile memory device

Method for measuring VT 's less than zero without applying negative voltages