Inventor
DUTARTRE DIDIER
FR47 patents
⚠️ This page may combine multiple inventors who share the name “DUTARTRE DIDIER”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
ST MICROELECTRONICS SA
25 patentsUS6177717B1Jan 23, 2001
Low-noise vertical bipolar transistor and corresponding fabrication process
ST MICROELECTRONICS SA62 citations93
US6537894B2Mar 25, 2003
Process for fabricating a substrate of the silicon-on-insulator or silicon-on-nothing type and resulting device
ST MICROELECTRONICS SA43 citations92
US6472262B2Oct 29, 2002
Method for fabricating a bipolar transistor of the self-aligned double-polysilicon type with a heterojunction base and corresponding transistor
ST MICROELECTRONICS SA23 citations91
US7906381B2Mar 15, 2011
Method for integrating silicon-on-nothing devices with standard CMOS devices
ST MICROELECTRONICS SA14 citations84
US9711550B2Jul 18, 2017
Pinned photodiode with a low dark current
ST MICROELECTRONICS SA9 citations83
US6744080B2Jun 1, 2004
Method of manufacturing a bipolar transistor of double-polysilicon, heterojunction-base type and corresponding transistor
ST MICROELECTRONICS SA15 citations83
US9929039B2Mar 27, 2018
Method for manufacture of a semiconductor wafer suitable for the manufacture of an SOI substrate, and SOI substrate wafer thus obtained
ST MICROELECTRONICS SA3 citations73
US6873088B2Mar 29, 2005
Vibratory beam electromechanical resonator
ST MICROELECTRONICS SA6 citations71
US6238941B1May 29, 2001
Characterizing of silicon-germanium areas on silicon
ST MICROELECTRONICS SA10 citations71
US6656812B1Dec 2, 2003
Vertical bipolar transistor having little low-frequency noise and high current gain, and corresponding fabrication process
ST MICROELECTRONICS SA8 citations70
US6162706ADec 19, 2000
Method of epitaxy on a silicon substrate comprising areas heavily doped with arsenic
ST MICROELECTRONICS SA6 citations70
US6583451B2Jun 24, 2003
Process for fabricating a network of nanometric lines made of single-crystal silicon and device obtained
ST MICROELECTRONICS SA3 citations63
US6642096B2Nov 4, 2003
Bipolar transistor manufacturing
ST MICROELECTRONICS SA6 citations62
US7892927B2Feb 22, 2011
Transistor with a channel comprising germanium
ST MICROELECTRONICS SA2 citations61
US7776745B2Aug 17, 2010
Method for etching silicon-germanium in the presence of silicon
ST MICROELECTRONICS SA4 citations60
US6642108B2Nov 4, 2003
Fabrication processes for semiconductor non-volatile memory device
ST MICROELECTRONICS SA4 citations60
US6776842B2Aug 17, 2004
Method of epitaxy on a silicon substrate comprising areas heavily doped with arsenic
ST MICROELECTRONICS SA4 citations59
US10535552B2Jan 14, 2020
Method for manufacture of a semiconductor wafer suitable for the manufacture of an SOI substrate, and SOI substrate wafer thus obtained
ST MICROELECTRONICS SA0 citations52
US9704903B2Jul 11, 2017
Front-side imager having a reduced dark current on SOI substrate
ST MICROELECTRONICS SA0 citations52
US9312408B2Apr 12, 2016
Imager having a reduced dark current through an increased bulk doping level
ST MICROELECTRONICS SA0 citations52
US7622368B2Nov 24, 2009
Forming of a single-crystal semiconductor layer portion separated from a substrate
ST MICROELECTRONICS SA0 citations51
US6852993B2Feb 8, 2005
Emission process for a single photon, corresponding semiconducting device and manufacturing process
ST MICROELECTRONICS SA0 citations51
US6294443B1Sep 25, 2001
Method of epitaxy on a silicon substrate comprising areas heavily doped with boron
ST MICROELECTRONICS SA0 citations48
US10262898B2Apr 16, 2019
Method for forming an electrical contact between a semiconductor film and a bulk handle wafer, and resulting structure
ST MICROELECTRONICS SA0 citations47
US6218723B1Apr 17, 2001
Integrated capacitor with high voltage linearity and low series resistance
ST MICROELECTRONICS SA0 citations46
ST MICROELECTRONICS CROLLES 2 SAS
7 patentsUS10978340B2Apr 13, 2021
Method for forming an electrical contact between a semiconductor film and a bulk handle wafer, and resulting structure
ST MICROELECTRONICS CROLLES 2 SAS2 citations68
US11978710B2May 7, 2024
Integrated circuit comprising a substrate equipped with a trap-rich region, and fabricating process
ST MICROELECTRONICS CROLLES 2 SAS0 citations62
US11757054B2Sep 12, 2023
Integrated optical sensor with pinned photodiodes
ST MICROELECTRONICS CROLLES 2 SAS0 citations62
US11075177B2Jul 27, 2021
Integrated circuit comprising a substrate equipped with a trap-rich region, and fabricating process
ST MICROELECTRONICS CROLLES 2 SAS0 citations62
US10263110B2Apr 16, 2019
Method of forming strained MOS transistors
ST MICROELECTRONICS CROLLES 2 SAS1 citations59
US11562927B2Jan 24, 2023
Method for forming an electrical contact between a semiconductor film and a bulk handle wafer, and resulting structure
ST MICROELECTRONICS CROLLES 2 SAS0 citations57
US10658578B2May 19, 2020
Memory cell comprising a phase-change material
ST MICROELECTRONICS CROLLES 2 SAS0 citations52
ST MICROELECTRONICS CROLLES 2
3 patentsUS8975154B2Mar 10, 2015
Process for producing at least one deep trench isolation
ST MICROELECTRONICS CROLLES 22 citations57
US7776679B2Aug 17, 2010
Method for forming silicon wells of different crystallographic orientations
ST MICROELECTRONICS CROLLES 21 citations52
US8975730B2Mar 10, 2015
Method for protection of a layer of a vertical stack and corresponding device
ST MICROELECTRONICS CROLLES 20 citations51
DUTARTRE DIDIER
3 patentsUS8158495B2Apr 17, 2012
Process for forming a silicon-based single-crystal portion
DUTARTRE DIDIER2 citations57
US8603887B2Dec 10, 2013
Method for depositing a silicon oxide layer of same thickness on silicon and on silicon-germanium
DUTARTRE DIDIER0 citations45
US8168536B2May 1, 2012
Realization of self-positioned contacts by epitaxy
DUTARTRE DIDIER0 citations39