Inventor
CHU TA-SHUN
TW20 patents
⚠️ This page may combine multiple inventors who share the name “CHU TA-SHUN”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
TRON FUTURE TECH INC
8 patentsUS11509320B2Nov 22, 2022
Signal converting apparatus and related method
TRON FUTURE TECH INC0 citations62
US11165435B2Nov 2, 2021
Signal converting apparatus
TRON FUTURE TECH INC1 citations62
US12543259B2Feb 3, 2026
Radio-frequency circuit for phased array antenna
TRON FUTURE TECH INC0 citations60
US11496142B2Nov 8, 2022
Signal distribution system, and related phased array radar system
TRON FUTURE TECH INC0 citations59
US11368161B2Jun 21, 2022
Signal divider, signal distribution system, and method thereof
TRON FUTURE TECH INC0 citations59
US12494808B2Dec 9, 2025
RF receiver and method for receiving RF input signal
TRON FUTURE TECH INC0 citations58
US12355477B2Jul 8, 2025
RF transmitter and method for emitting RF output signal
TRON FUTURE TECH INC0 citations58
US12174243B2Dec 24, 2024
Probe assembly, system and method for testing rf device of phased array antenna
TRON FUTURE TECH INC1 citations57
CHAO YUAN-JU
4 patentsUS9774337B1Sep 26, 2017
High speed SAR ADC using comparator output triggered binary-search timing scheme and bit-dependent DAC settling
CHAO YUAN-JU16 citations92
US9843336B1Dec 12, 2017
System and method of minimizing differential non-linearity (DNL) for high resolution current steering DAC
CHAO YUAN-JU7 citations83
US9866236B1Jan 9, 2018
Appapatus and method for fast conversion, compact, ultra low power, wide supply range auxiliary digital to analog converters
CHAO YUAN-JU3 citations72
US9621180B1Apr 11, 2017
Apparatus and method for fast conversion, compact, ultra low power, wide supply range auxiliary digital to analog converters
CHAO YUAN-JU2 citations72
CHAO YUAN JU
3 patentsUS9979382B1May 22, 2018
Programmable duty-cycle low jitter differential clock buffer
CHAO YUAN JU11 citations83
US10128860B1Nov 13, 2018
High speed SAR ADC using comparator output triggered binary-search timing scheme and bit-dependent DAC settling
CHAO YUAN JU1 citations51
US10014874B1Jul 3, 2018
System and method of minimizing differential non-linearity (DNL) for high resolution current steering DAC
CHAO YUAN JU0 citations51