Inventor
JEFFERSON DAVID E
US20 patents
⚠️ This page may combine multiple inventors who share the name “JEFFERSON DAVID E”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
ALTERA CORP
17 patentsUS6292016B1Sep 18, 2001
Programmable logic with on-chip DLL or PLL to distribute clock
ALTERA CORP93 citations99
US6215326B1Apr 10, 2001
Programmable logic device architecture with super-regions having logic regions and a memory region
ALTERA CORP331 citations99
US6130552AOct 10, 2000
Programmable logic integrated circuit with on-chip DLL or PLL for clock distribution
ALTERA CORP105 citations99
US5963069AOct 5, 1999
System for distributing clocks using a delay lock loop in a programmable logic circuit
ALTERA CORP142 citations99
US5744991AApr 28, 1998
System for distributing clocks using a delay lock loop in a programmable logic circuit
ALTERA CORP216 citations99
US6107820AAug 22, 2000
Redundancy circuitry for programmable logic devices with interleaved input circuits
ALTERA CORP101 citations98
US5850152ADec 15, 1998
Programmable logic array integrated circuit devices
ALTERA CORP69 citations97
US5850151ADec 15, 1998
Programmable logic array intergrated circuit devices
ALTERA CORP47 citations96
US6657456B1Dec 2, 2003
Programmable logic with on-chip DLL or PLL to distribute clock
ALTERA CORP18 citations92
US6337578B2Jan 8, 2002
Redundancy circuitry for programmable logic devices with interleaved input circuits
ALTERA CORP16 citations92
US6115312ASep 5, 2000
Programmable logic device memory cell circuit
ALTERA CORP19 citations84
US6222382B1Apr 24, 2001
Redundancy circuitry for programmable logic devices with interleaved input circuits
ALTERA CORP14 citations82
US7236411B1Jun 26, 2007
Programmable memory access parameters
ALTERA CORP9 citations73
US6480028B2Nov 12, 2002
Programmable logic device architectures with super-regions having logic regions and memory region
ALTERA CORP5 citations73
US7397726B1Jul 8, 2008
Flexible RAM clock enable
ALTERA CORP3 citations63
US6879183B2Apr 12, 2005
Programmable logic device architectures with super-regions having logic regions and a memory region
ALTERA CORP2 citations63
US7864603B1Jan 4, 2011
Memory elements with leakage compensation
ALTERA CORP1 citations51