Inventor

JAVORKA PETER

DE63 patents

⚠️ This page may combine multiple inventors who share the name “JAVORKA PETER”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

JAVORKA PETER

GLOBALFOUNDRIES INC

Multi-gate FETs having corrugated semiconductor stacks and method of forming the same

Method of forming a semiconductor structure including an implantation of ions into a layer of spacer material

Method for forming a transistor comprising high-k metal gate electrode structures including a polycrystalline semiconductor material and embedded strain-inducing semiconductor alloys

Contact geometry having a gate silicon length decoupled from a transistor length

Method of forming a semiconductor device structure and such a semiconductor device structure

Three-dimensional transistor with improved channel mobility

Methods of removing gate cap layers in CMOS applications

Method for forming a semiconductor device and semiconductor device structures

Transistor with embedded Si/Ge material having reduced offset and superior uniformity

Full silicidation prevention via dual nickel deposition approach

Method of forming a semiconductor structure comprising a formation of at least one sidewall spacer structure

FDSOI channel control by implanted high-k buried oxide

Three-dimensional transistor with improved channel mobility

FDSOI channel control by implanted high-K buried oxide

Enhancing transistor performance and reliability by incorporating deuterium into a strained capping layer

FINFET doping method with curvilnear trajectory implantation beam path

Efficient main spacer pull back process for advanced VLSI CMOS technologies

HK/MG process flows for P-type semiconductor devices

Integrated inductor

Method for reducing defects of gate of CMOS devices during cleaning processes by modifying a parasitic PN junction

Method for creating tensile strain by selectively applying stress memorization techniques to NMOS transistors

Performance enhancement in transistors by providing an embedded strain-inducing semiconductor material on the basis of a seed layer

Superior integrity of high-k metal gate stacks by preserving a resist material above end caps of gate electrode structures

Methods for fabricating semiconductor devices

Semiconductor device having stressed etch stop layers of different intrinsic stress in combination with PN junctions of different design in different device regions

KRONHOLZ STEPHAN

Transistor with embedded Si/Ge material having reduced offset and superior uniformity

Methods of epitaxially forming materials on transistor devices

Methods of forming isolation structures for semiconductor devices

Reduction of defect rates in PFET transistors comprising a Si/Ge semiconductor material formed by epitaxial growth

Strain enhancement in transistors comprising an embedded strain-inducing semiconductor alloy by corner rounding at the top of the gate electrode

Enhancing deposition uniformity of a channel semiconductor alloy by forming a recess prior to the well implantation

JAVORKA PETER

Performance enhancement in transistors by providing an embedded strain-inducing semiconductor material on the basis of a seed layer

Differential threshold voltage adjustment in PMOS transistors by differential formation of a channel semiconductor material

Transistor with boot shaped source/drain regions

Partial poly amorphization for channeling prevention

Full silicidation prevention via dual nickel deposition approach

Reduced threshold voltage-width dependency and reduced surface topography in transistors comprising high-k metal gate electrode structures by a late carbon incorporation

ADVANCED MICRO DEVICES INC

Technique for providing stress sources in transistors in close proximity to a channel region by recessing drain and source regions

Technique for forming a strained transistor by a late amorphization and disposable spacers

Method of making a semiconductor device comprising isolation trenches inducing different types of strain

Technique for enhancing stress transfer into channel regions of NMOS and PMOS transistors

FLACHOWSKY STEFAN

Method of increasing the germanium concentration in a silicon-germanium layer and semiconductor device comprising same

THEES HANS-JUERGEN

Methods of forming PEET devices with different structures and performance characteristics

KAMMLER THORSTEN

Leakage control in field effect transistors based on an implantation species introduced locally at the STI edge

KRONHOLZ STEPHAN-DETLEF

Superior integrity of high-k metal gate stacks by preserving a resist material above end caps of gate electrode structures

TAN CHUNG FOONG

Method of forming transistor with increased gate width

GLOBALFOUNDRIES US INC

Transistor with phase transition material region between channel region and each source/drain region

SCHEIPER THILO

Methods of forming metal silicide regions on semiconductor devices using different temperatures

GERHARDT MARTIN

Shallow source and drain architecture in an active region of a semiconductor device having a pronounced surface topography by tilted implantation

WEI ANDY

Technique for providing stress sources in transistors in close proximity to a channel region by recessing drain and source regions