Inventor

YOSHIDA TOYOHIKO

JP97 patents

⚠️ This page may combine multiple inventors who share the name “YOSHIDA TOYOHIKO”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

YOSHIDA TOYOHIKO

MITSUBISHI ELECTRIC CORP

Data processor having an instruction decoder and a plurality of executing units for performing a plurality of operations in parallel

MOS integrated circuit device operating with low power consumption

Data processor and method of processing data

MOS integrated circuit device operating with low power consumption

Data processor having an instruction decoder and a plurality of executing units for performing a plurality of operations in parallel

Data processing having incircuit emulation function

Data processor calculating branch target address of a branch instruction in parallel with decoding of the instruction

Data processor having 2n bits width data bus for context switching function

Apparatus for a multi-data store or load instruction for transferring multiple contiguous storage locations in one transfer operation

Pipeline processor, with return address stack storing only pre-return processed addresses for judging validity and correction of unprocessed address

Data processor with selectively enabled and disabled branch prediction operation

System for processing data having different formats

Preceding instruction address based branch prediction in a pipelined processor

Data processor

Data processor having an instruction decoder

Combined Instruction and address caching system using independent buses

Data processing system capable of executing groups of instructions, including at least one arithmetic instruction, in parallel

Compressed image decompressing device

Memory apparatus and data processor using the same

Memory apparatus and data processor using the same

Memory apparatus and data processor using the same

Data processor including a decoding unit for decomposing a multifunctional data transfer instruction into a plurality of control codes

Pipeline processor, with a return address stack and two stack pointers, for storing pre-return processed addresses

Pipelined data processor for floating point and integer operation with exception handling

Microprocessor implementing single-step or sequential microcode execution while in test mode

Data processor capable of execution of plural instructions in parallel

Multiprocessor including system for pipeline processing of multi-functional instructions

Integrated circuit device and microprocessor constituted thereby

Self-testing microprocessor with microinstruction substitution

Microprocessor having program counter registers for its coprocessors

Pipelined microprocessor with instruction execution control unit which receives instructions from separate path in test mode for testing instruction execution pipeline

Pipelined multi-stage data processor including an operand bypass mechanism

Pipelined computer

Instruction fetching in data processing apparatus

MOS transistor circuit for shared precharging of bus lines

Microprocessor for controlling the conditional execution of instructions

Microprocessor capable of executing condition execution instructions using encoded condition execution field in the instructions

Data processing device

Data processor that utilizes full data width when processing a string operation

Integrated circuit with reduced clock skew and divided power supply lines

Improved pipelined processor with two stage decoder for exchanging register values for similar operand instructions

Branch target and next instruction address calculation in a pipeline processor

Data processor with pipeline which disables exception processing for non-taken branches

Microprocessor having delayed instructions

RENESAS TECH CORP

Data processor having 2n bits width data bus for context switching functions

Semiconductor integrated circuit device and electronic system for executing data processing by using memory

Data processing device

Selective conversion to native code using hardware translator, software translator, and software interpreter

Data processing device with instruction translator and memory interface device to translate non-native instructions into native instructions for processor

Image signal transcoder capable of bit stream transformation suppressing deterioration of picture quality