Inventor · disambiguated record
Michael A. Kazda
Also filed as: KAZDA MICHAEL · KAZDA MICHAEL A · KAZDA MICHAEL ANTHONY
10 granted patents·2 pending applications·129 citations·filing 2007–2023
85Inventor score
Top patents by PatentIndex Score
12 records- 0194US8635577B2Timing refinement re-routingKAZDA MICHAEL ANTHONY·Filed 2012·Granted Jan 21, 2014·87 cites·17 claims
- 0292US7581201B2System and method for sign-off timing closure of a VLSI chipIBM·Filed 2007·Granted Aug 25, 2009·35 cites·19 claims
- 0380US11080456B2Automated design closure with abutted hierarchyIBM·Filed 2019·Granted Aug 3, 2021·4 cites·17 claims
- 0473US10078722B2Dynamic microprocessor gate design tool for area/timing margin controlIBM·Filed 2016·Granted Sep 18, 2018·2 cites·18 claims
- 0560US9075948B2Method of improving timing critical cells for physical design in the presence of local placement congestionIBM·Filed 2013·Granted Jul 7, 2015·1 cites·20 claims
- 0660US2025077888A1Predicting local layout effects using a variational autoencoder with integrated regression and classification networkIBM·Filed 2023·Application pending·0 cites
- 0754US10671791B2Dynamic microprocessor gate design tool for area/timing margin controlIBM·Filed 2018·Granted Jun 2, 2020·0 cites·18 claims
- 0852US12282721B2Netlist design for post silicon local clock controller timing improvementIBM·Filed 2022·Granted Apr 22, 2025·0 cites·20 claims
- 0951US10831967B1Local clock buffer controller placement and connectivityIBM·Filed 2019·Granted Nov 10, 2020·0 cites·20 claims
- 1047US10606976B2Engineering change order aware global routingIBM·Filed 2017·Granted Mar 31, 2020·0 cites·20 claims
- 1147US2010257503A1Post-routing coupling fixes for integrated circuitsIBM·Filed 2009·Application pending·0 cites
- 1244US10831965B1Placement of vectorized latches in hierarchical integrated circuit developmentIBM·Filed 2019·Granted Nov 10, 2020·0 cites·14 claims
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